參數(shù)資料
型號： ORT42G5-1BM484I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 68/119頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 4CH 484-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 60
系列： *
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
52
Test Modes
In addition to the operational logic described in the preceding sections, the Embedded Core contains logic to sup-
port various test modes - both for device validation and evaluation and for operating system level tests. The follow-
ing sections discuss two of the test support logic blocks, supporting various loopback modes and SERDES
characterization.
Loopback Testing
Loopback testing is performed by looping back (either internal to the Embedded Core, by conguring the FPGA
logic or by external connections) transmitted data to the corresponding receiver inputs, or received data to the
transmitter output. The loopback path may be either serial or parallel.
In general, loopback tests can be classied as “near end” or “far end.” In “near end” loopback (Figure 32(a)), data is
generated and checked locally, i.e. by logic on, or connection of, test equipment to the same card as the FPSC. In
“far end” loopback (Figure 32(b)), the generating and checking functions are performed remotely, either by test
equipment or a remote system card.
Figure 32. “Near End” vs. “Far End” Loopback
The loopback mode can also be characterized by the physical location of the loopback connection. There are three
possible loopback modes supported by the Embedded Core logic:
High-speed serial loopback at the CML buffer interface (near end)
Parallel loopback at the SERDES boundary (far end)
Device Under Test (DUT)
CML
Buffer
CML
Buffer
HDIN[P:N]_xx
2
Non-Functional
Embedded Core
FPGA Logic
40
MRWDxx[39:0]
32
4
Receive
Transmit
TWDxx[31:0]
TCOMMAxx[3:0]
TBIT9xx[3:0]
HDOUT[P:N]_xx
2
Data
Checking
Data
Generation
n
m
{
Active
(to Eye Diagram
Measurement or
remote System
Card)
Test Equipment
or Logic on Local
System Card
(a) “Near End” Loopback
High Speed
Serial Loopback
Connection
Device Under Test (DUT)
Data
Generation
Data
Checking
2
HDIN[P:N]_xx
HDOUT[P:N]_xx
{
n
m
Non-Functional
Active
(to Logic on
Local System
Card)
(b) “Far End” Loopback
FPGA Logic
40
MRWDxx[39:0]
Receive
4
Transmit
TWDxx[31:0]
TCOMMAxx[3:0]
TBIT9xx[3:0]
32
DE
MUX
8B/10B SERDES
CML
Buffer
8B/10B
CML
Buffer
SERDES Block
Parallel
Loopback
Connection
SERDES
Embedded Core
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT42G5-1BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT42G5-1BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT42G5-2BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT42G5-2BM484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT42G5-2BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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