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參數(shù)資料
| 型號： | ORT42G5-1BM484I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 67/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 4CH 484-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
51
Start Up Sequence for the ORT82G5
The following sequence is required by the ORT82G5 device. For information required for simulation that may be dif-
ferent than this sequence, see the ORT82G5 Design Kit.
1.
Initiate a hardware reset by making PASB_RESETN low. Keep this low during FPGA conguration of the
device. The device will be ready for operation 3 ms after the low to high transition of PASB_RESETN.
2.
Congure the following SERDES internal and external registers. Note that after device initialization, all alarm
and status bits should be read once to clear them. A subsequent read will provide the valid state. Set the fol-
lowing bits in register 30800:
– Bits LCKREFN_[AA:AD] to 1, which implies lock to data.
– Bits ENBYSYNC_[AA:AD] to 1 which enables dynamic alignment to comma.
Set the following bits in register 30801:
– Bits LOOPENB_[AA:AD] to 1 if high-speed serial loopback is desired.
Set the following bits in register 30900:
– Bits LCKREFN_[BA:BD] to 1 which implies lock to data.
– Bits ENBYSYNC_[BA:BD] to 1 which enables dynamic alignment to comma.
Set the following bits in register 30901:
– Bits LOOPENB_[BA:BD] to 1 if high-speed serial loopback is desired.
Set the following bits in registers 30002, 30012, 30022, 30032, 30102, 30112, 30122, 30132:
– TXHR set to 1 if TX half-rate is desired.
– 8B10BT set to 1
Set the following bits in registers 30003, 30013, 30023, 30033, 30103, 30113, 30123, 30133:
– RXHR Set to 1 if RX half-rate is desired.
– 8B10BR set to 1.
– LINKSM set to 1 if the Fibre Channel state machine is desired.
Assert GSWRST bit by writing two 1’s. Deassert GSWRST bit by writing two 0’s. Wait 3ms. If higher speed
serial loopback has been selected, the receive PLLs will use this time to lock to the new serial data.
Monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30100, 30110, 30120, 30130:
– LKI, PLL lock indicator. 1 indicates that PLL has achieved lock.
3. If 8b/10b mode is enabled, enable link synchronization by periodically sending the following sequence three
times:
– K28.5 D21.4 D21.5 D21.5 or any other idle ordered set (starting with a /comma/) in FC mode.
– /comma/ characters for the XAUI state machine and /A/ characters for word and channel alignment in XAUI
mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT42G5-1BMN484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT42G5-1BMN484I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT42G5-2BM484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT42G5-2BM484I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT42G5-2BMN484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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