- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄11731 > ORT42G5-1BM484I (Lattice Semiconductor Corporation)IC FPSC TRANSCEIVER 4CH 484-BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | ORT42G5-1BM484I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 53/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 4CH 484-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)當(dāng)前第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
39
TCK78[A:B]:
This is a muxed output from the core to the FPGA across the core-FPGA interface of one of the 2 transmit SER-
DES clocks per block operating at up to 92.5 MHz in the embedded core. There is one clock output per SERDES
block.
TSYS_CLK[AC, AD, BC, BD]:
These clocks are inputs to the SERDES block A and B respectively from the FPGA. These are used by each chan-
nel to control the timing of the Transmit Data Path. To guarantee correct transmit operation theses clocks must be
frequency locked within 0 ppm to TCK78[A:B].
Transmit and Receive Clock Rates
Table 13 shows typical relationship between the data rates, the reference clock, the transmit TCK78[A:B] clock and
the receive RCK78[A:B] clock. The selection of full-rate or half-rate for a given reference clock speed is set by bits
in the transmit and receive control registers and can be set per channel.
Table 13. Transmit Data and Clock Rates
Besides taking in a TSYS_CLK_xx from the FPGA logic for each channel, the transmit path logic sends back a
clock of the same frequency, but arbitrary phase. This clock, TCK78[A:B], is derived from the MUX block of one of
the 2 channels in its SERDES block. The MUX blocks provide the potential source for TCK78[A:B] by a divide-by-4
of the SERDES STBC311xs clock used in synchronizing the transmit data words in the STBC311xx clock domain.
The STBC311xx clocks are internal to the core and are not brought across the core/FPGA interface
The receiver section receives high-speed serial data at its differential CML input port and sends in to the Clock and
Data Recovery (CDR) block. The CDR block then generates a recovered clock (RWCKxx) and retimes the data.
Thus, the recovered receive clocks are asynchronous between channels.
Transmit Clock Source Selection
The TCKSEL[A:B] bit select the source channel of TCK78[A:B]. The selection of the source for TCK78[A:B] is con-
trolled by this bit as shown in Table 14.
Table 14. TCK78[A:B] Source Selection
Recommended Transmit Clock Distribution for the ORT42G5
As an example of the recommended clock distribution approach, TSYS_CLK_A[C or D] can be sourced by TCK78A
as shown in Figure 18 if the transmit line rate are common for both channels in a block. Similar clocking would be
used for Block B.
Data Rate
Reference Clock
TCK78[A: B] and RCK78[A:B]
Clocks
Rate of Channel
Selected as Clock
Source
0.6 Gbps
60 MHz
15 MHz
Half
1.0 Gbps
100 MHz
25 MHz
Half
1.25 Gbps
125 MHz
31.25 MHz
Half
2.0 Gbps
100 MHz
50 MHz
Full
2.5 Gbps
125 MHz
62.5 MHz
Full
3.125 Gbps
156 MHz
78 MHz
Full
3.7 Gbps
185 MHz
92.5 MHz
Full
TCKSEL[A:B]
Clock Source
0
Channel C
1
Channel D
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GRM1885C1H561JA01D | CAP CER 560PF 50V 5% NP0 0603 |
| ORT42G5-1BM484C | IC FPSC TRANSCEIVER 4CH 484-BGA |
| PIC17C43-25/P | IC MCU OTP 4KX16 PWM 40DIP |
| ORSO82G5-2F680I | IC FPSC TRANSCEIVER 8CH 680-BGA |
| ORSO82G5-2F680C | IC FPSC TRANSCEIVER 8CH 680-BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORT42G5-1BMN484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT42G5-1BMN484I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT42G5-2BM484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT42G5-2BM484I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT42G5-2BMN484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。