參數資料
型號： ORT42G5-1BM484I
廠商： Lattice Semiconductor Corporation
文件頁數： 58/119頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 4CH 484-BGA
產品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 60
系列： *
Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
43
Internal Clock Signals at the FPGA/Core Interface for the ORT82G5
There are several clock signals dened at the FPGA/Embedded Core interface in addition to the external reference
clock for each SERDES quad. All of the ORT82G5 clock signals are shown in Figure 24 and are described follow-
ing the gure.
Figure 24. ORT82G5 Clock Signals (High Speed Serial I/O Also Shown)
REFCLKP_[A:B], REFCLKN_[A:B]:
These are the differential reference clocks provided to the ORT82G5 device as described earlier. They are used as
the reference clock for both TX and RX paths. For operation of the serial links at 3.125 Gbps, the reference clocks
will be at a frequency of 156.25 MHz.
RWCK[AA:BD]:
These are the low-speed receive clocks from the embedded core to the FPGA across the core-FPGA interface.
These are derived from the recovered low-speed complementary clocks from the SERDES blocks. RWCK_AA
belongs to Channel AA, RWCK_AB belongs to channel AB and so on. With a reference clock input of 156.25 MHz,
these clocks operate at 78.125 MHz.
RCK78[A:B]:
These are muxed outputs of RWCKA[A:D] and RWCKB[B:D] respectively. With a reference clock input of 156.25
MHz, these clocks operate at 78.125 MHz.
FPGA
Logic
Common Logic, Quad A
Channel AA
Channel AB
Channel AD
Channel AC
Common Logic, Quad B
Channel BA
Channel BB
Channel BD
Channel BC
RCK78A
TCK78A
RSYS_CLK_A1
TSYS_CLK_AA
RWCKAA
RWCKAB
TSYS_CLK_AB
RWCKAC
TSYS_CLK_AC
RSYS_CLK_A2
TSYS_CLK_AD
RWCKAD
RCK78B
TCK78B
RSYS_CLK_B1
TSYS_CLK_BA
RWCKBA
RWCKBB
TSYS_CLK_BB
RSYS_CLK_B2
RWCKBD
RWCKBC
TSYS_CLK_BC
TSYS_CLK_BD
REFCLK[P:N]_A
2
HDIN[P:N]_AC
2
HDOUT[P:N]_AD
HDIN[P:N]_AD
2
HDOUT[P:N]_AC
HDOUT[P:N]_AB
2
HDIN[P:N]_AB
2
HDOUT[P:N]_AA
2
HDIN[P:N]_AA
2
REFCLK[P:N]_B
HDIN[P:N]_BC
2
HDIN[P:N]_BD
2
HDIN[P:N]_BB
2
HDIN[P:N]_BA
2
HDOUT[P:N]_BA
HDOUT[P:N]_BB
HDOUT[P:N]_BC
HDOUT[P:N]_BD
2
TCK78A
Backplane
Serial
Link
相關PDF資料
PDF描述
GRM1885C1H561JA01D CAP CER 560PF 50V 5% NP0 0603
ORT42G5-1BM484C IC FPSC TRANSCEIVER 4CH 484-BGA
PIC17C43-25/P IC MCU OTP 4KX16 PWM 40DIP
ORSO82G5-2F680I IC FPSC TRANSCEIVER 8CH 680-BGA
ORSO82G5-2F680C IC FPSC TRANSCEIVER 8CH 680-BGA
相關代理商/技術參數
參數描述
ORT42G5-1BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT42G5-1BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT42G5-2BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT42G5-2BM484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT42G5-2BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*