L
G
R
Serial Communications Interface (SCI)
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
138
Serial Communications Interface (SCI)
MOTOROLA
RE — Receiver Enable
When the receiver enable bit is set, the receiver is enabled. When RE
is clear, the receiver is disabled and all of the status bits associated
with the receiver (RDRF, IDLE, OR, NF and FE) are inhibited. While
the receiver is enabled, the Port C bit 6 is forced to be an input.
RWU — Receiver Wake-up
When the receiver wake-up bit is set by the user software, it puts the
receiver to sleep and enables the wake-up function. If the WAKE bit
is cleared, RWU is cleared by the SCI logic after receiving 10 (M = 0)
or 11 (M = 1) consecutive ones. If the WAKE bit is set, RWU is cleared
by the SCI logic after receiving a data word whose MSB is set.
SBK — Send Break
If the send break bit is toggled set and cleared, the transmitter sends
10 (M = 0) or 11 (M = 1) zeros and then reverts to idle sending data.
If SBK remains set, the transmitter will continually send whole blocks
of zeros (sets of 10 or 11) until cleared. At the completion of the break
code, the transmitter sends at least one high bit to guarantee
recognition of a valid start bit. If the transmitter is currently empty and
idle, setting and clearing SBK is likely to queue two character times of
break because the first break transfers almost immediately to the shift
register and the second is then queued into the parallel transmit
buffer.
11.8.4 Serial Communications Status Register (SCSR)
The serial communications status register (SCSR) provides inputs to the
interrupt logic circuits for generation of the SCI system interrupt.
$004A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TDRE
TC
RDRF
IDLE
OR
NF
FE
0
Write:
Reset:
1
1
0
0
0
0
0
0
Figure 11-10. SCI Status Register (SCSR)