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Serial Communications Interface (SCI)
General Release Specification
MC68HC(7)05H12
—
Rev. 1.0
140
Serial Communications Interface (SCI)
MOTOROLA
the receive shift register to the receive data register is inhibited in the
case of overrun. The FE bit is set during the same cycle as the RDRF
bit but does not get set in the case of an overrun (OR). The framing
error flag inhibits further transfer of data into the receive data register
until it is cleared.
11.8.5 Baud Rate Register (BAUD)
The baud rate register (BAUD) is used to set the bit rate for the SCI
system. Normally this register is written once, during initialization, to set
the baud rate for SCI communications. Both the receiver and the
transmitter use the same baud rate which is derived from the MCU bus
rate clock. A two stage divider is used to develop custom baud rates from
normal MCU crystal frequencies so it is not necessary to use special
baud rate crystal frequencies.
TCLR — Clear Baud Rate Counters (for test purposes only)
This bit is disabled and remains low in any mode other than test or
bootstrap mode. Reset clears this bit. While in test or bootstrap mode,
setting this bit causes the baud rate counter chains to be reset. The
logic one state of this bit is transitory and reads always return a logic
zero. This control bit is intended only for factory testing of the MCU.
SPP — SPI Prescaler bit
1 =
SCI receiver clock connected to the SPI clock
input.
bus clock connected to the SPI clock input.
The SCI baud rate can be calculated from the internal bus clock and
the two prescaler factors PRS1 and PRS2. The first prescaler factor
PRS1 is selected with SCP0 and SCP1, as shown in
Table 11-1
. The
0 =
$004B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
SPP
SCP1
SCP0
0
SCR2
SCR1
SCR0
Write:
TCLR
RCKB
Reset:
1
1
0
0
0
U
U
U
Figure 11-11. SCI Baud Rate Register (BAUD)