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參數(shù)資料
| 型號(hào)： | P610ARM-FPNR |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | General purpose 32-bit microprocessor |
| 中文描述： | 通用32位微處理器 |
| 文件頁(yè)數(shù)： | 106/173頁(yè) |
| 文件大小： | 897K |
| 代理商： | P610ARM-FPNR |
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Memory Management Unit
ARM610 Data Sheet
9-2
9.1
Memory Management Unit (MMU)
The MMU performs two primary functions: it translates virtual addresses into physical
addresses, and it controls memory access permissions. The MMU hardware required
to perform these functions consists of a Translation Look-aside Buffer (TLB), access
control logic, and translation table walking logic.
The MMU supports memory accesses based on Sections or Pages. Sections are
comprised of 1MB blocks of memory. Two different page sizes are supported: Small
Pages consist of 4Kb blocks of memory and Large Pages consist of 64Kb blocks of
memory. (Large Pages are supported to allow mapping of a large region of memory
while using only a single entry in the TLB). Additional access control mechanisms are
extended within Small Pages to 1Kb Sub-Pages and within Large Pages to 16Kb Sub-
Pages.
The MMU also supports the concept of domains—areas of memory that can be
defined to possess individual access rights. The Domain Access Control Register is
used to specify access rights for up to 16 separate domains.
The TLB caches 32 translated entries. During most memory accesses, the TLB
provides the translation information to the access control logic.
If the TLB contains a translated entry for the virtual address, the access control logic
determines whether access is permitted. If access is permitted, the MMU outputs the
appropriate physical address corresponding to the virtual address. If access is not
permitted, the MMU signals the CPU to abort.
If the TLB misses (ie. does not contain a translated entry for the virtual address), the
translation table walk hardware is invoked to retrieve the translation information from
a translation table in physical memory. Once retrieved, the translation information is
placed into the TLB, possibly overwriting an existing value. The entry to be overwritten
is chosen by cycling sequentially through the TLB locations.
When the MMU is turned off (as happens on reset), the virtual address is output
directly onto the physical address bus.
9.2
MMU Program Accessible Registers
The ARM610 Processor provides several 32-bit registers which determine the
operation of the MMU. The format for these registers is shown in
register summary
on page -3. A brief description of the registers is provided below.
Each register will be discussed in more detail within the section that describes its use.
·
Figure 0-1: MMU
Data is written to and read from the MMU's registers using the ARM CPU's MRC and
MCR coprocessor instructions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P610ARM-B | General purpose 32-bit microprocessor |
| P610ARM-KG | General purpose 32-bit microprocessor |
| P610ARM-KW | General purpose 32-bit microprocessor |
| P6121-AU120 | Incremental Encoders |
| P6111-AP120 | Incremental Encoders |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P610ARM-KG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| P610ARM-KW | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:General purpose 32-bit microprocessor |
| P6-10R | 制造商:Panduit Corp 功能描述:PANDUIT |
| P6-10R-E | 功能描述:端子 NON-INSL.RING #6 #10 RoHS:否 制造商:AVX 產(chǎn)品:Junction Box - Wire to Wire 系列:9826 線規(guī):26-18 接線柱/接頭大小: 絕緣: 顏色:Red 型式:Female 觸點(diǎn)電鍍:Tin over Nickel 觸點(diǎn)材料:Beryllium Copper, Phosphor Bronze 端接類型:Crimp |
| P610R-E | 制造商:Panduit Corp 功能描述: |
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