參數(shù)資料
型號(hào): P610ARM-FPNR
廠商: Zarlink Semiconductor Inc.
英文描述: General purpose 32-bit microprocessor
中文描述: 通用32位微處理器
文件頁數(shù): 111/173頁
文件大小: 897K
代理商: P610ARM-FPNR
Memory Management Unit
ARM610 Data Sheet
9-7
9.7
Section Descriptor
Bits 4:2 (U,C, & B)
control the cache- and write-buffer-related functions as follows:
U - Updateable
operation to maintain consistency with external memory (if the cache is enabled).
: indicates that the data in the cache should be updated during a write
C - Cacheable
cache is enabled).
: indicates that data at this address will be placed in the cache (if the
B - Bufferable
buffer (if the write buffer is enabled).
: indicates that data at this address will be written through the write
Bits 8:5
Control Register) that contain the primary access controls.
specify one of the sixteen possible domains (held in the Domain Access
Bits 11:10 (AP)
shown in
dependent upon the setting of the S bit (Control Register bit 8). Note that the Domain
Access Control specifies the primary access control; the AP bits only have an effect in
client mode. Refer to section on access permissions.
specify the access permissions for this section and are interpreted as
Table 9-2: Interpreting access permission (AP) Bits
·
. Their interpretation is
Bits 19:12
are always written as 0.
Bits 31:20
form the corresponding bits of the physical address for the 1Mb section.
AP
S
Supervisor
permissions
User
permissions
Notes
00
0
No Access
No Access
Any access generates a permission fault
00
1
Read Only
No Access
Supervisor read only permitted
01
x
Read/Write
No Access
Access allowed only in Supervisor mode
10
x
Read/Write
Read Only
Writes in User mode cause permission fault
11
x
Read/Write
Read/Write
All access types permitted in both modes.
Table 9-2: Interpreting access permission (AP) Bits
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