參數(shù)資料
型號(hào)： PCD5002AH
廠商： NXP SEMICONDUCTORS
元件分類： 尋呼電路
英文描述： Enhanced Pager Decoder for APOC1/POCSAG
中文描述： TELECOM, PAGING DECODER, PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁(yè)數(shù)： 16/48頁(yè)
文件大?。?/td> 252K
代理商： PCD5002AH
1999 Jan 08
16
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Code-words received at the expected sync word positions
(POCSAG batch size) are matched against standard
POCSAG sync word, all enabled UPSWs and preamble.
Data output to an external controller is initiated by an
interrupt at the next sync word position, after reception of
16 code-words.
The call header preceding the data has a different
structure from normal POCSAG or APOC1 data. The data
header format is shown in Table 12.
Continuous data decoding continues until one of the
following conditions occur:
The decoder is switched to the OFF state
A Forced Call Termination (FCT) command is received
via the I
2
C-bus
Preamble is detected at the sync word position
Standard POCSAG sync word or an enabled non-CDD
sync word is detected.
Only a forced call termination command will be indicated in
the SRAM data by a call terminator. In the other events
continuous data decoding will stop without notification.
Upon forced termination the ‘fade recovery’ mode is
entered. Detection of preamble causes the device to
switch to the ‘preamble receive’ mode. Detection of a
standard sync word or any enabled non-continuous UPSW
will cause the device to switch to the ‘data receive’ mode.
Continuous data decoding will continue in the next batch if
any enabled CDD sync word is detected or no enabled
sync word is detected. It should be noted that the
enhanced call termination is ignored in CCD mode.
8.21
Receiver and oscillator control
A paging receiver and an RF oscillator circuit can be
controlled independently via enable outputs RXE and ROE
respectively. Their operating periods are optimized
according to the synchronization mode of the decoder.
Each enable signal has its own programmable
establishment time (see Table 14).
Table 12
Continuous data header format
Table 13
Data header bit identification
Table 14
Receiver and oscillator establishment times (note 1)
Note
1.
The exact values may differ slightly from the above values, depending on the bit rate (see Table 25).
BYTE NUMBER
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
1
2
3
0
0
X
X
C3
X
X
C2
F0
X
C1
F1
C3
C3
E3
C2
C2
E2
C1
C1
E1
0
0
0
BITS (MSB TO LSB)
IDENTIFICATION
C3 to C1
F0 and F1
E3 to E1
identifier number of continuous data decoding sync word
function bits of received address code-word (bits 20 and 21)
detected error type (see Table 11); E3 = 0 in a concatenated call header
CONTROL OUTPUT
ESTABLISHMENT TIME
UNIT
RXE
ROE
5
10
30
15
40
30
50
ms
ms
20
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