參數(shù)資料
型號: PCD5002AH
廠商: NXP SEMICONDUCTORS
元件分類: 尋呼電路
英文描述: Enhanced Pager Decoder for APOC1/POCSAG
中文描述: TELECOM, PAGING DECODER, PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁數(shù): 24/48頁
文件大小: 252K
代理商: PCD5002AH
1999 Jan 08
24
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
8.35
Received call delay
Call reception (detection of an enabled RIC) causes both the periodic interrupt modulus and the counter register to be
reset.
Since the periodic interrupt counter runs for another 2.55 s after a reset, the received call delay (in
1
100
s units) can be
determined by reading the counter register.
Table 21
Alert set-up register (04H; write)
Note
1.
Bits D7 and D6 correspond to function bits 20 and 21 respectively in the address code-word, which designate the
POCSAG call type as shown in Table 1.
BIT (MSB D7)
VALUE
DESCRIPTION
D0
0
1
0
1
0
1
1
1
1
call alert via cadence register
POCSAG call alert (pattern selected by D7 and D6)
LOW level acoustic alert (ATL), pulsed vibrator alert (25 Hz)
HIGH level acoustic alert (ATL + ATH), continuous vibrator alert
normal alerts (acoustic and LED)
warbled alerts: 16 Hz (LED: on/off, ATL/ATH: alternate f
AWH
, f
AWL
)
acoustic alerts enable (ATL, ATH)
vibrator alert enabled (VIB)
LED alert enabled (LED)
POCSAG alert pattern FC = 00; see Fig.10 (a)
POCSAG alert pattern FC = 01; see Fig.10 (b)
POCSAG alert pattern FC = 10; see Fig.10 (c)
POCSAG alert pattern FC = 11; see Fig.10 (d)
D1
D2
D3
D4
D5
D7 and D6
(1)
0 0
0 1
1 0
1 1
Fig.10 POCSAG alert patterns.
handbook, full pagewidth
MLC251
(a)
(b)
(c)
(d)
D7, D6
0 1
1 0
1 1
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