參數(shù)資料
型號: PCD5002AH
廠商: NXP SEMICONDUCTORS
元件分類: 尋呼電路
英文描述: Enhanced Pager Decoder for APOC1/POCSAG
中文描述: TELECOM, PAGING DECODER, PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁數(shù): 5/48頁
文件大?。?/td> 252K
代理商: PCD5002AH
1999 Jan 08
5
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
7
PINNING
SYMBOL PIN
DESCRIPTION
ATL
ALC
1
2
alert LOW level output
alert control input (normally LOW by
internal pull-down)
direct ON/OFF input (normally LOW by
internal pull-down)
real-time clock frequency reference
output
interrupt output
not connected
reset input (normally LOW by internal
pull-down)
external positive voltage reference
input
I
2
C-bus serial data input/output
I
2
C-bus serial clock input
main positive supply voltage
main negative supply voltage
voltage converter positive output
voltage converter shunt capacitor
(positive side)
voltage converter shunt capacitor
(negative side)
DON
3
REF
4
INT
n.c.
RST
5
6
7
V
PR
8
SDA
SCL
V
DD
V
SS
V
PO
CCP
9
10
11
12
13
14
CCN
15
TS1
16
test input 1 (normally LOW by internal
pull-down)
decoder crystal oscillator output
decoder crystal oscillator input
not connected
test input 2 (normally LOW by internal
pull-down)
battery sense input
demodulator quick charge output
received data input (POCSAG or
APOC1)
receiver circuit enable output
receiver oscillator enable output
synthesizer serial data output
synthesizer serial clock output
synthesizer latch enable output
main negative supply voltage
vibrator motor drive output
LED drive output
alert HIGH level output
XTAL2
XTAL1
n.c.
TS2
17
18
19
20
BAT
DQC
RDI
21
22
23
RXE
ROE
ZSD
ZSC
ZLE
V
SS
VIB
LED
ATH
24
25
26
27
28
29
30
31
32
SYMBOL PIN
DESCRIPTION
Fig.2 Pin configuration.
handbook, full pagewidth
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
1
1
1
1
1
1
1
3
3
3
2
2
2
2
2
A
L
V
Z
Z
Z
R
S
S
S
V
C
C
T
ATL
ALC
DON
REF
INT
n.c.
RST
RXE
RDI
DQC
BAT
TS2
n.c.
XTAL1
XTAL2
PCD5002AH
MGL564
V
V
VPR
V
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參數(shù)描述
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