參數(shù)資料
型號(hào): PCD5002AH
廠商: NXP SEMICONDUCTORS
元件分類: 尋呼電路
英文描述: Enhanced Pager Decoder for APOC1/POCSAG
中文描述: TELECOM, PAGING DECODER, PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁(yè)數(shù): 29/48頁(yè)
文件大?。?/td> 252K
代理商: PCD5002AH
1999 Jan 08
29
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Table 23
Special programmed functions (EEPROM address 00H)
Table 24
Special programmed functions (EEPROM address 01H)
Note
1.
Since the exact establishment time is related to the programmed bit rate, Table 25 shows the values for the various
bit rates.
BIT (MSB: D7)
VALUE
DESCRIPTION
D0
0
1
0
1
POCSAG decoding enabled
APOC1 decoding enabled
cycle length: 5 batches
cycle length: 15 batches
batch number (D1 = 0; MSB is ignored)
batch number (D1 = 1)
continuous data decoding enabled
received data inversion enabled
D1
D5 to D2 (MSB D5)
0 to 4
0 to 14
1
1
D6
D7
BIT (MSB: D7)
VALUE
DESCRIPTION
D1 and D0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
1
5 ms receiver establishment time (nominal); note 1
10 ms receiver establishment time (nominal); note 1
15 ms receiver establishment time (nominal); note 1
30 ms receiver establishment time (nominal); note 1
20 ms oscillator establishment time (nominal); note 1
30 ms oscillator establishment time (nominal); note 1
40 ms oscillator establishment time (nominal); note 1
50 ms oscillator establishment time (nominal); note 1
512 bits/s received bit rate
1024 bits/s (not used in POCSAG)
1200 bits/s
2400 bits/s
synthesizer interface enabled (programming at switch-on)
voltage converter enabled
D3 and D2
D5 and D4
D6
D7
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