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參數(shù)資料
| 型號(hào)： | PCD5002AH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 尋呼電路 |
| 英文描述： | Enhanced Pager Decoder for APOC1/POCSAG |
| 中文描述： | TELECOM, PAGING DECODER, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32 |
| 文件頁數(shù)： | 21/48頁 |
| 文件大小： | 252K |
| 代理商： | PCD5002AH |
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1999 Jan 08
21
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Table 16
Index register
Notes
1.
2.
The index register only uses the least significant nibble, the upper 4 bits are ignored.
Writing to registers 0B to 0F has no effect, reading produces meaningless data.
ADDRESS
(1)
REGISTER FUNCTION
ACCESS
00H
00H
01H
02H
03H
04H
05H
05H
06H
07H
08H
09H
0AH
status
control
R
W
real-time clock: seconds
real-time clock:
1
100
second
alert cadence
alert set-up
periodic interrupt modulus
periodic interrupt counter
RAM write address pointer
EEPROM address pointer
RAM read address pointer
RAM data output
EEPROM data input/output
unused
R/W
R/W
W
W
W
R
R
R/W
R/W
R
R/W
note 2
0BH to 0FH
8.28
External interrupt
The PCD5002A can signal events to an external controller
via an interrupt signal at output INT. The interrupt polarity
is programmable via SPF programming. The interrupt
source is shown in the status register.
Interrupts are generated by the following events (more
than one event is possible):
Call data available for output (bit D2)
SRAM pointers becoming equal (bit D3)
Expiry of periodic time-out (bit D7)
Expiry of alert time-out (bit D4)
Change of state in out-of-range indicator (bit D5)
Change of state in battery-low indicator or in receiver
control output RXE (bit D6).
Immediate interrupts are generated by status bits D3,
D4, D6 (RXE monitoring) and D7. Bits D2, D5 and D6
(BAT monitoring) generate interrupts as soon as the
receiver is disabled (RXE = 0).
When call data is available (D2 = 1) but the receiver
remains switched on, an interrupt is generated at the next
sync word position, if data fail mode (short fade recovery
mode in APOC1) is not active.
The interrupt output INT is reset after completion of a
status read operation.
8.29
Interrupt masking
In the PCD5002A certain interrupts can be suppressed by
masking via the control register. The following interrupts
can be masked:
Out-of-Range (status bit D5)
: change of state
interrupt, masked by setting control register bit D5
BAT/RXE monitoring (status bit D6)
: change of state
interrupt (source selected by control register bit D2),
masked by setting control register bit D6
Periodic Timer (status bit D7)
: timer overflow interrupt,
masked by setting control register bit D7.
Although no interrupts are generated by these conditions
when masked via the control register, the corresponding
status bits are updated normally and available via the
status register. At reset the control register is cleared,
causing all interrupts to be enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCD5002H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder |
| PCD5002HBD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002HBD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder |
| PCD5003 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
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