參數(shù)資料
型號(hào)： PCD5002H
廠商： NXP SEMICONDUCTORS
元件分類： 尋呼電路
英文描述： Advanced POCSAG and APOC-1 Paging Decoder
中文描述： TELECOM, PAGING DECODER, PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁(yè)數(shù)： 32/48頁(yè)
文件大?。?/td> 203K
代理商： PCD5002H
1997 Jun 24
32
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
9
OPERATING INSTRUCTIONS
9.1
Reset conditions
When the PCD5002 is reset by applying a HIGH level to
input RST, the condition of the decoder is as follows:
OFF status (irrespective of DON input level)
REF output frequency 32768 Hz
All internal counters reset
Status/control register reset
INT output at LOW level
No alert transducers selected
LED, VIB and ATH outputs at LOW level
ATL output high-impedance
SDA and SCL inputs high-impedance
Voltage converter disabled.
The programmed functions are activated within t
RSU
after
release of the reset condition (RST LOW). The settings
affecting the external operation of the PCD5002 are as
follows:
REF output frequency
Voltage converter
INT output polarity
Signal test mode.
When input DON is HIGH, the decoder starts operating in
ON status immediately following t
RSU
.
9.2
Power-on reset circuit
During power-up of the PCD5002 a HIGH level of
minimum duration t
RST
= 50
μ
s must be applied to pin
RST. This is to prevent EEPROM corruption which might
otherwise occur because of the undefined contents of the
Control register.
The reset signal can be applied by the external
microcontroller or by an RC power-on reset circuit on pin
RST (C to V
PR
, R to V
SS
). Such an RC-circuit should have
a time constant of at least 3t
RST
= 150
μ
s.
Input RST has an internal high-ohmic pull-down resistor
(nominal 2 M
at 2.5 V supply) which could be used
together with a suitable external capacitor connected to
V
PR
to create a power-on reset signal. However, since this
pull-down resistor varies considerably with processing and
supply voltage, the resulting time constant is inaccurate.
A more accurate reset duration can be realised with an
additional external resistor connected to V
SS
.
Recommended minimum values in this case are
C = 2.2 nF and R = 100 k
(see Fig.16).
9.3
Reset timing
The start-up time for the crystal oscillator may exceed 1 s
(typ. 800 ms). It is advisable to apply a reset condition, at
least during the first part of this period. The minimum reset
pulse duration t
RST
is 50
μ
s.
During reset the oscillator is active, but clock signals are
inhibited internally. Once the reset condition is released
the end of the oscillator start-up period can be detected by
a rising edge on output INT.
During a reset the voltage converter clock (V
clk
) is held at
zero. The resulting output voltage drop may cause
problems when the external resetting device is powered by
the internal voltage doubler. A sufficiently large buffer
capacitor connected between output V
PO
and V
SS
must be
provided to supply the microcontroller during reset.
The voltage at V
PO
will not drop below V
DD
0.7 V.
Immediately after a reset all programmable internal
functions will start operating according to a programmed
value of 0. During the first 8 full clock cycles (t
RSU
) all
programmed values are loaded from EEPROM.
After reset the receiver outputs RXE and ROE become
active immediately, if DON is HIGH and the synthesizer is
disabled. When the synthesizer is enabled, RXE and ROE
will only become active after the second pulse on ZLE
completes the loading of synthesizer data.
The full reset timing is illustrated in Fig.12. The start-up
timing including synthesizer programming is illustrated in
Fig.13.
9.4
Initial programming
A newly-delivered PCD5002 has EEPROM contents which
are undefined. The EEPROM should therefore be
programmed, followed by a reset to activate the SPF
settings, before any attempt is made to use the device.
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