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參數(shù)資料
| 型號： | PCD5002H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 尋呼電路 |
| 英文描述： | Advanced POCSAG and APOC-1 Paging Decoder |
| 中文描述： | TELECOM, PAGING DECODER, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32 |
| 文件頁數(shù)： | 8/48頁 |
| 文件大?。?/td> | 203K |
| 代理商： | PCD5002H |
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1997 Jun 24
8
Philips Semiconductors
Product specification
Advanced POCSAG and APOC-1 Paging
Decoder
PCD5002
Table 1
POCSAG recommended call types and function bits
BIT 20 (MSB)
BIT 21 (LSB)
CALL TYPE
DATA FORMAT
0
0
1
1
0
1
0
1
numeric
alert only 1
alert only 2
alphanumeric
4-bits per digit
7-bits per ASCII character
The POCSAG standard only allows combinations of data
formats and function code bits as given in Table 1.
However, other (non-standard) combinations will be
decoded normally by the PCD5002.
8.4
Error correction
In the PCD5002 error correction methods have been
implemented as shown in Table 2.
Random error correction is default for both address and
message codewords. In addition, burst error correction
can be enabled by SPF programming. Up to 3 erroneous
bits in a 4-bit burst can be corrected.
The error type detected for each codeword is identified in
the message data output to the microcontroller, allowing
rejection of calls with too many errors.
Table 2
Error correction
8.5
Operating states
The PCD5002 has 2 operating states:
ON status
OFF status.
The operating state is determined by a Direct Control input
(DON) and bit D4 in the control register (see Table 3).
ITEM
CORRECTION
Preamble
Synchronization
codeword
Address codeword
4 random errors in 31 bits
2 random errors in 32 bits
2 random errors, plus 4-bit burst
errors (optional)
2 random errors, plus 4-bit burst
errors (optional)
Message codeword
Table 3
Truth table for decoder operating status
8.6
ON status
In the ON status the decoder pulses the receiver and
oscillator enable outputs (RXE and ROE respectively)
according to the code structure and the synchronization
algorithm. Data received serially at the data input (RDI) is
processed for call reception.
The data protocol can be POCSAG or APOC-1.
Continuous data decoding upon reception of a special
sync word is also supported. The data protocol is selected
by SPF programming.
Reception of a valid paging call is signalled to the
microcontroller by an interrupt signal. The received
address and message data can then be read via the
I
2
C-bus interface.
8.7
OFF status
In the OFF status the decoder will neither activate the
receiver or oscillator enable outputs, nor process any data
at the data input. The crystal oscillator remains active to
permit communication with the microcontroller.
In both operating states an accurate timing reference is
available via the REF output. Using SPF programming the
signal periodicity may be selected as 32.768 kHz, 50 Hz,
2 Hz or
1
60
Hz.
8.8
Reset
The decoder can be reset by applying a positive pulse on
input pin RST. For successful reset at power-on, a HIGH
level must be present on the RST pin while the device is
powering-up
.
DON
INPUT
CONTROL
BIT D4
OPERATING STATUS
0
0
1
1
0
1
0
1
OFF
ON
ON
ON
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| PCB1 | Fuse |
| PCB2 | Fuse |
| PCB2.5 | Fuse |
| PCB3 | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
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| PCD5002HBD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002HBD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder |
| PCD5003 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5003A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for POCSAG |
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