MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8 Electrical Characteristics F" />
參數(shù)資料
型號(hào)： PCF52274CLU120
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 13/46頁(yè)
文件大?。?/td> 0K
描述： MCU 32-BIT W/LCD TOUCH 176-LQFP
標(biāo)準(zhǔn)包裝： 40
系列： MCF5227x
核心處理器： Coldfire V2
芯體尺寸： 32-位
速度： 120MHz
連通性： CAN，EBI/EMI，I²C，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，LCD，PWM，WDT
輸入/輸出數(shù)： 47
程序存儲(chǔ)器類型： ROMless
RAM 容量： 128K x 8
電壓 - 電源 (Vcc/Vdd)： 1.4 V ~ 1.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 176-LQFP
包裝： 托盤(pán)
MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor
20
5.6
ASP Electrical Characteristics
Table 12 lists the electrical specifications for the ASP module.
13
Discrete load capacitance for XTAL
Discrete load capacitance for EXTAL
CL_XTAL
CL_EXTAL
—2
× (C
L –
CS_XTAL –
CS_EXTAL –
CS_PCB)
7
pF
14
Frequency un-LOCK Range
fUL
–4.0
4.0
% fsys
15
Frequency LOCK Range
fLCK
–2.0
2.0
% fsys
17
CLKOUT period jitter 4, 5, 8 measured at fsys max
Peak-to-peak jitter (Clock edge to clock edge)
Long-term jitter
Cjitter
—
10
TBD
% fsys/2
19
VCO frequency (fvco = fref × PFDR)
fvco
350
540
MHz
1 Although these are the allowable frequency ranges, do not violate the VCO frequency range of the PLL. See the
MCF5227x Reference Manual for more details.
2 The minimum system frequency is the minimum input clock divided by the maximum low-power divider
(16 MHz
÷ 32,768). When the PLL is enabled, the minimum system frequency (f
sys) is 37.5 MHz.
3 This parameter is guaranteed by characterization before qualification rather than 100% tested. Applies to external clock
reference only.
4 Proper PC board layout procedures must be followed to achieve specifications.
5 This parameter is guaranteed by design rather than 100% tested.
6 This specification is the PLL lock time only and does not include oscillator start-up time..
7
CS_PCB is the measured PCB stray capacitance on EXTAL and XTAL.
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase
the Cjitter percentage for a given interval.
Table 12. ASP Electrical Characteristics
Characteristic
Symbol
Min
Typical
Max
Unit
ASP Analog Supply Voltage
VDDA
3.0
—
3.6
V
Input Voltage Range
VADIN
0—
VDDA
V
Operating Current Consumption
IDDA_ON
—
700
—
uA
Power-down Current Consumption
IDDA_OFF
—1
—
uA
Resolution
RES
——12
bits
Sampling rate
—
125
kS/s
Integral Non-linearity
INL
—
±8
±24
lsb1
Differential Non-linearity
DNL
—
±2
±24
ADC Internal Clock Frequency
tAIC
2—
8
MHz
Conversion Range
RAD
0—
VDDA
V
Table 11. PLL Electrical Characteristics (continued)
Num
Characteristic
Symbol
Min
Max
Unit
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