MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8 F" />
參數資料
型號: PCF52274CLU120
廠商: Freescale Semiconductor
文件頁數: 22/46頁
文件大小: 0K
描述: MCU 32-BIT W/LCD TOUCH 176-LQFP
標準包裝: 40
系列: MCF5227x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 120MHz
連通性: CAN,EBI/EMI,I²C,SPI,SSI,UART/USART,USB OTG
外圍設備: DMA,LCD,PWM,WDT
輸入/輸出數: 47
程序存儲器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 1.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 176-LQFP
包裝: 托盤
Electrical Characteristics
MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
29
5.8
General Purpose I/O Timing
Figure 16. GPIO Timing
5.9
Reset and Configuration Override Timing
Table 17. GPIO Timing1
1 These general purpose specifications apply to the following signals: IRQn, all UART signals, FlexCAN signals, PWM
signals, DACKn and DREQn, and all signals configured as GPIO.
Num
Characteristic
Symbol
Min
Max
Unit
G1
FB_CLK High to GPIO Output Valid
tCHPOV
—10
ns
G2
FB_CLK High to GPIO Output Invalid
tCHPOI
1.5
ns
G3
GPIO Input Valid to FB_CLK High
tPVCH
9—
ns
G4
FB_CLK High to GPIO Input Invalid
tCHPI
1.5
ns
Table 18. Reset and Configuration Override Timing
Num
Characteristic
Symbol
Min
Max
Unit
R1
RESET Input valid to FB_CLK High
tRVCH
9—
ns
R2
FB_CLK High to RESET Input invalid
tCHRI
1.5
ns
R3
RESET Input valid Time 1
1 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to
the system. Thus, RESET must be held a minimum of 100 ns.
tRIVT
5—
tCYC
R4
FB_CLK High to RSTOUT Valid
tCHROV
—10
ns
R5
RSTOUT valid to Config. Overrides valid
tROVCV
0—
ns
R6
Configuration Override Setup Time to RSTOUT invalid
tCOS
20
tCYC
R7
Configuration Override Hold Time after RSTOUT invalid
tCOH
0—
ns
R8
RSTOUT invalid to Configuration Override High Impedance
tROICZ
—1
tCYC
G1
FB_CLK
GPIO Outputs
G2
G3
G4
GPIO Inputs
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