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參數(shù)資料
| 型號： | PCF52274CLU120 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 17/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 32-BIT W/LCD TOUCH 176-LQFP |
| 標準包裝： | 40 |
| 系列： | MCF5227x |
| 核心處理器： | Coldfire V2 |
| 芯體尺寸： | 32-位 |
| 速度： | 120MHz |
| 連通性： | CAN，EBI/EMI，I²C，SPI，SSI，UART/USART，USB OTG |
| 外圍設備： | DMA，LCD，PWM，WDT |
| 輸入/輸出數(shù)： | 47 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 128K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.4 V ~ 1.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 176-LQFP |
| 包裝： | 托盤 |
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MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor
24
Figure 11. SDR Write Timing
SD8 SD_DQS[3:2] input hold relative to SD_CLK
tDQISDCH
Does not apply. 0.5
×SD_CLK fixed
width.
6
SD9 Data (D[31:0]) Input Setup relative to SD_CLK (reference
only)
tDVSDCH
0.25
×
SD_CLK
—ns
7
SD10 Data Input Hold relative to SD_CLK (reference only)
tDISDCH
1.0
—
ns
SD11 Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid
tSDCHDMV
—0.5
× SD_CLK
+ 2
ns
SD12 Data (D[31:0]) and Data Mask (SD_DQM[3:0]) Output Hold
tSDCHDMI
1.5
—
ns
1 The device supports same frequency of operation for both FlexBus and SDRAM clock operates as that of the internal bus clock.
Please see the PLL chapter of the device reference manual for more information on setting the SDRAM clock rate.
2 SD_CLK is one SDRAM clock in ns.
3 Pulse width high plus pulse width low cannot exceed min and max clock period.
4 SD_SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle
variation from this guideline is expected. SD_SDR_DQS will only pulse during a read cycle and one pulse will occur for each
data beat.
5 SD_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle
variation from this guideline is expected. SD_DQS will only pulse during a read cycle and one pulse will occur for each data
beat.
6 The SD_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does
not affect the memory controller.
7 Since a read cycle in SDR mode still uses the DQS circuit within the device, it is critical that the data valid window be centered
1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup spec is
provided as guidance.
Table 14. SDR Timing Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
Notes
SD_CLK
SDDM
D[31:0]
A[23:0]
SD_BA[1:0]
CMD
ROW
SD1
SD4
COL
SD5
WD1
WD2
WD3
WD4
SD12
SD11
SD_CSn
SD_RAS
SD_WE
SD_CAS
SD2
SD3
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