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參數(shù)資料
| 型號： | PCF52274CLU120 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 43/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 32-BIT W/LCD TOUCH 176-LQFP |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | MCF5227x |
| 核心處理器： | Coldfire V2 |
| 芯體尺寸： | 32-位 |
| 速度： | 120MHz |
| 連通性： | CAN，EBI/EMI，I²C，SPI，SSI，UART/USART，USB OTG |
| 外圍設(shè)備： | DMA，LCD，PWM，WDT |
| 輸入/輸出數(shù)： | 47 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 128K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.4 V ~ 1.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 176-LQFP |
| 包裝： | 托盤 |
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MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8
Hardware Design Considerations
Freescale Semiconductor
6
3.3
ADC Power Filtering
To minimize noise, an external filters is required for the ADCVDD power pin. The filter shown in Figure 4 should be connected
between the board EVDD and the ADCVDD pin. The resistor and capacitors should be placed as close to the dedicated ADCVDD
pin as possible.
Figure 4. ADC VDD Power Filter
3.4
Supply Voltage Sequencing
The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. Both SDVDD (2.5V
or 3.3V) and EVDD are specified relative to IVDD.
3.4.1
Power Up Sequence
If EVDD/SDVDD are powered up with IVDD at 0 V, then the sense circuits in the I/O pads will cause all pad output drivers
connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up
before IVDD must powered up. IVDD should not lead the EVDD, SDVDD or PLLVDD by more than 0.4 V during power ramp-up,
or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than
500 us to avoid turning on the internal ESD protection clamp diodes.
3.4.2
Power Down Sequence
If IVDD/PLLVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high
impedance state. There is no limit on how long after IVDD and PLLVDD power down before EVDD or SDVDD must power
down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there will be
undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1.
Drop IVDD/PLLVDD to 0 V.
2.
Drop EVDD/SDVDD supplies.
Board EVDD
0
Ω
0.1 F
ADC VDD Pin
10 F
GND
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