Pin Assignments and Reset States
MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
13
ALLPST
—
O
EVDD
76
—
JTAG_EN
—
D
I
EVDD
79
K10
PSTCLK
—
TCLK
—
U
O
EVDD
74
P8
DSI
—
TDI
—
U
I
EVDD
78
M11
DSO
—
TDO
—
O
EVDD
81
L11
BKPT
—TMS
—
U
I
EVDD
80
N11
DSCLK
—
TRST
—U
I
EVDD
77
P11
Test
TEST
—
D
I
EVDD
134
E10
Power Supplies
IVDD
—
39, 75, 114, 138,
171
K5, F10, E5, J10
EVDD
—
12, 72, 73, 94, 111,
148, 176
E6, E7, F5, F6, G5,
H9, J9, K8, K9
SD_VDD
—
14, 43, 44, 70, 113,
132, 146
E8, E9, F9, G9, H5,
J5, J6, K6, K7
VDD_OSC
—
108
G13
VDD_PLL
—
104
H14
VDD_USB
—
151
B10
VDD_RTC
—
101
J13
VDD_ADC
—
91
L13
VSS
—
1, 13, 45, 71, 93,
112, 133, 147
F7, F8, G6–G8,
H6–H8, J7, J8
VSS_OSC
—
107
H13
VSS_ADC
—
92
L14
1 Pull-ups are generally only enabled on pins with their primary function, except as noted.
2 Refers to pin’s primary function.
3 Enabled only in oscillator bypass mode (internal crystal oscillator is disabled).
4 GPIO functionality is determined by the edge port module. The GPIO module is only responsible for assigning the alternate functions.
5 Pull-up when DREQ controls the pin.
6 The 176 LQFP device only supports a 12-bit LCD data bus.
7 DSPI or SBF signal functionality is controlled by RESET. When asserted, these pins are configured for serial boot; when negated, the
pins are configured for DSPI.
8 Pull-up when the serial boot facility (SBF) controls the pin.
Table 6. MCF5227x Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate 1
Alternate 2
Pull-up
(U)
1
Pu
ll-d
o
wn
(D)
Dir
ection
2
Vo
lt
a
g
e
D
o
m
a
in
MCF52274
176 LQFP
MCF52277
196 MAPBGA