參數(shù)資料
型號: PCI1620GHK
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 147/164頁
文件大?。?/td> 720K
代理商: PCI1620GHK
7
7
7.14 Interrupt Line Register
This read/write register is programmed by the system and indicates to the software which interrupt line the firmware
loading function of PCI1620 is connected to. The default value of this register is FFh, indicating that an interrupt line
has not yet been assigned to the function.
Bit
7
6
5
4
3
2
1
0
Name
Interrupt line
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
1
1
1
1
1
1
1
1
Register:
Offset:
Type:
Default:
Interrupt line
3Ch
Read/Write
FFh
7.15 Interrupt Pin Register
This register defaults to 00h.
Bit
7
6
5
4
3
2
1
0
Name
Interrupt pin
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Interrupt pin
3Dh
Read-only
00h
7.16 Min Grant Register
This read/write register can be used by host BIOS to assign a latency timer register value to PCI1620.
Bit
7
6
5
4
3
2
1
0
Name
Min grant
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
1
1
1
Register:
Offset:
Type:
Default:
Min grant
3Eh
Read/Write
07h
7.17 Max Latency Register
This read/write register may be used by host BIOS to assign an arbitration priority level to PCI1620.
Bit
7
6
5
4
3
2
1
0
Name
Max latency
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
1
0
0
Register:
Offset:
Type:
Default:
Max latency
3Fh
Read/Write
04h
相關PDF資料
PDF描述
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
PCI9054AB50BI Interface IC
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