參數(shù)資料
型號： PCI1620GHK
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 96/164頁
文件大?。?/td> 720K
代理商： PCI1620GHK
4
–
28
4.40 Card Control Register
The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register, and the
enable bit is shared between functions 0 and 1. See Table 4
–
15 for a complete description of the register contents.
The RI_OUT signal is enabled through this register, and the enable bit is shared between functions 0 and 1.
Bit
7
6
5
4
3
2
1
0
Name
Card control
Type
RW
RW
RW
R
R
RW
RW
RW
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Card control
91h
Read-only, Read/Write
00h
Table 4
–
15. Card Control Register Description
BIT
7
SIGNAL
TYPE
FUNCTION
RIENB
RW
Ring indicate enable. When this bit is 1, the RI_OUT output is enabled. This bit defaults to 0.
6
ZVENABLE
RW
Compatibility ZV mode enable. When this bit is 1, the corresponding PC Card socket interface ZV
terminals enter a high-impedance state. This bit defaults to 0.
5
PORT_SEL
RW
Port select. This bit controls the priority for the ZV_SEL0 and ZV_SEL1 signaling if bit 6 (ZVENABLE) is
set in both functions.
0 = Socket 0 takes priority, as signaled through ZV_SEL0, when both sockets are in ZV mode.
1 = Socket 1 takes priority, as signaled through ZV_SEL1, when both sockets are in ZV mode.
Reserved. These bits default to 0.
4
–
3
RSVD
R
2
AUD2MUX
RW
CardBus audio-to-MFUNC. When this bit is set, the CAUDIO CardBus signal is routed to the
corresponding MFUNC terminal, which may be configured for CAUDWPM. When both socket 0 and
socket 1 functions have AUD2MUX set, socket 0 takes precedence.
0 = CAUDIO to SPKROUT (default)
1 = CAUDIO to MFUNC
1
SPKROUTEN
RW
When bit 1 is set, the SPKR termijnal from the PC Card is enabled and is routed to tthe SPKROUT terminal.
The SPKR signal from socket 0 is XORed with the SPKR signal from socket 1 and sent to SPKROUT. The
SPKROUT terminal drives data only when the SPKROUTEN bit of either function is set. This bit is encoded
as:
0 = SPKR to SPKROUT not enabled (default)
1 = SPKR to SPKROUT enabled
0
IFG
RW
Interrupt flag. This bit is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. This bit is set when
a functional interrupt is signaled from a PC Card interface, and is socket dependent (i.e., not global). Write
back a 1 to clear this bit.
0 = No PC Card functional interrupt detected (default)
1 = PC Card functional interrupt detected
This bit is global in nature and should be accessed only through function 0.
相關(guān)PDF資料
PDF描述
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
PCI9054AB50BI Interface IC
相關(guān)代理商/技術(shù)參數(shù)
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