參數(shù)資料
型號： PCI1620GHK
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 86/164頁
文件大?。?/td> 720K
代理商： PCI1620GHK
4
–
18
4.31 System Control Register
System-level initializations are performed through programming this doubleword register. Some of the bits are global
in nature and should be accessed only through function 0. See Table 4
–
7 for a complete description of the register
contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
System control
Type
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
System control
Type
RW
RW
R
R
R
R
R
R
R
RW
RW
RW
RW
R
RW
RW
Default
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
Register:
Offset:
Type:
Default:
System control
80h (Functions 0, 1)
Read-only, Read/Write
0044 9060h
Table 4
–
7. System Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
31
–
30
SER_STEP
RW
Serial input stepping. In serial PCI interrupt mode, these bits are used to configure the serial stream PCI
interrupt frames, and can be used to accomplish an even distribution of interrupts signaled on the four PCI
interrupt slots.
00 = INTA/INTB signal in INTA/INTB slots (default)
01 = INTA/INTB signal in INTB/INTC slots
10 = INTA/INTB signal in INTC/INTD slots
11 = INTA/INTB signal in INTD/INTA slots
29
INTRTIE
RW
This bit ties INTA to INTB internally (to INTA), and reports this through the interrupt pin register (PCI offset
3Dh, see Section 4.24). This bit has no effect on INTC or INTD.
28
RSVD
R
Reserved. Bit 28 returns 0 when read.
27
P2CCLK
RW
P2C power switch CLOCK. This bit determines whether the CLOCK terminal (PDV 154 or GHK F15) is
an input that requires an external clock source or if this terminal is an output that uses the internal oscillator.
Bit 27 can be set to enable the PCI1620 to generate and drive CLOCK from the PCI clock.
0 = CLOCK provided externally, input to PCI1620 (default)
1 = CLOCK generated by PCI clock and driven by PCI1620
26
SMIROUTE
RW
SMI interrupt routing. This bit is shared between functions 0 and 1, and selects whether IRQ2 or CSC is
signaled when a write occurs to power a PC Card socket.
0 = PC Card power change interrupts are routed to IRQ2 (default).
1 = A CSC interrupt is generated on PC Card power changes.
25
SMISTATUS
RW
SMI interrupt status. This socket-dependent bit is set when a write occurs to set the socket power, and
the SMIENB bit is set. Writing a 1 to this bit clears the status.
0 = SMI interrupt is signaled.
1 = SMI interrupt is not signaled.
24
SMIENB
RW
SMI interrupt mode enable. When this bit is set, the SMI interrupt signaling generates an interrupt when
a write to the socket power control occurs. This bit is shared and defaults to 0 (disabled).
0 = SMI interrupt mode is disabled (default).
1 = SMI interrupt mode is enabled.
These bits are global in nature and should be accessed only through function 0.
相關(guān)PDF資料
PDF描述
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
PCI9054AB50BI Interface IC
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