參數(shù)資料
型號: PCI1620GHK
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù): 156/164頁
文件大?。?/td> 720K
代理商: PCI1620GHK
8
4
8.5
Operating Free-Air Temperature (see Note 5, Figure 8
1, and Figure 8
4)
PCI Timing Requirements Over Recommended Ranges of Supply Voltage and
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
tpd
Propagation delay time
Pro agation delay time
(see Note 4)
PCLK-to-shared signal
valid delay time
tval
CL = 50 pF,
CL = 50 F,
See Note 5
11
ns
PCLK-to-shared signal
invalid delay time
tinv
2
ten
tdis
tsu
th
NOTES:
Enable time, high impedance-to-active delay time from PCLK
ton
toff
tsu
th
2
ns
Disable time, active-to-high impedance delay time from PCLK
28
ns
Setup time before PCLK valid
7
ns
Hold time after PCLK high
0
ns
4. PCI shared signals are AD31
AD0, C/BE3
C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
5. This data manual uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript
A
indicates the
type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup
time, and th = hold time.
8.6
Switching Characteristics for PHY-Link Interface
PARAMETER
MEASURED
50% to 50%
MIN
6
TYP
MAX
UNIT
tsu
th
td
Setup time, Dn, CTLn, LREQ to PHY_CLK
Hold time, Dn, CTLn, LREQ before PHY_CLK
50% to 50%
1
ns
Delay time, PHY_CLK to Dn, CTLn
50% to 50%
2
11
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