參數(shù)資料
型號： PCI1620GHK
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 34/164頁
文件大小： 720K
代理商： PCI1620GHK
2
–
18
Table 2
–
12. CardBus PC Card Address and Data Terminals (Slots A and B)
TERMINAL
NUMBER
I/O
DESCRIPTION
NAME
SLOT A
PDV
SLOT B
PDV
GHK
GHK
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
151
149
148
146
145
136
135
134
131
129
127
125
123
122
121
104
102
103
101
100
99
98
97
94
93
89
90
87
88
85
86
84
E19
G15
F18
G14
G17
J14
J17
J18
K15
K18
L14
L17
L19
M19
M18
W16
R14
U15
V15
P14
W15
U14
R13
P13
U13
P12
R12
V12
U12
R11
W12
P11
82
79
78
77
76
67
66
65
63
60
59
57
55
54
53
36
34
35
33
32
31
30
28
26
25
21
22
19
20
17
18
16
V11
R10
U10
V10
W10
R08
W07
V07
P08
V06
U06
V05
R06
U05
W04
M03
M01
M02
L05
L06
L03
L02
K06
K03
K02
J03
J05
J01
J02
H02
H01
H03
I/O
CardBus address and data. These signals make up the multiplexed CardBus address
and data bus on the CardBus interface. During the address phase of a CardBus cycle,
CAD31
–
CAD0 contain a 32-bit address. During the data phase of a CardBus cycle,
CAD31
–
CAD0 contain data. CAD31 is the most significant bit.
CC/BE3
CC/BE2
CC/BE1
CC/BE0
132
120
105
96
K14
M17
T19
V14
64
52
37
27
U07
T01
M06
K05
I/O
CardBus bus commands and byte enables. CC/BE3
–
CC/BE0 are multiplexed on the
same CardBus terminals. During the address phase of a CardBus cycle,
CC/BE3
–
CC/BE0 define the bus command. During the data phase, this 4-bit bus is used
as byte enables. The byte enables determine which byte paths of the full 32-bit data bus
carry meaningful data. CC/BE0 applies to byte 0 (CAD7
–
CAD0), CC/BE1 applies to
byte 1 (CAD15
–
CAD8), CC/BE2 applies to byte 2 (CAD23
–
CAD8), and CC/BE3 applies
to byte 3 (CAD31
–
CAD24).
CPAR
107
P15
40
N02
I/O
CardBus parity. In all CardBus read and write cycles, the PCI1620 calculates even parity
across the CADx and CC/BEx buses. As an initiator during CardBus cycles, the PCI1620
outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the PCI1620
compares its calculated parity to the parity indicator of the initiator; a compare error
results in a parity error assertion.
Terminal name for slot A is preceded with A_. For example, the full name for terminals 107 and P15 are A_CPAR.
Terminal name for slot B is preceded with B_. For example, the full name for terminals 40 and N02 are B_CPAR.
相關(guān)PDF資料
PDF描述
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
PCI9054AB50BI Interface IC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCI1620PDV 功能描述:外圍驅(qū)動器與原件 - PCI PC Card Flash & Smart Card Cntrlr RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PCI-1620U 制造商:ADVANTECH 制造商全稱:Advantech Co., Ltd. 功能描述:8-port RS-232 PCI Communication Card, with Surge Protection
PCI1620ZHK 功能描述:外圍驅(qū)動器與原件 - PCI PC Card Flash & Smart Card Cntrlr RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PCI-1622A-BE 制造商:Advantech Co Ltd 功能描述:8PORT RS-422/485 PCI COM CARD - Trays 制造商:Advantech Co Ltd 功能描述:8-port RS-422/485 UPCI COMM card
PCI-1622CU 制造商:ADVANTECH 制造商全稱:Advantech Co., Ltd. 功能描述:8-port RS-422/485 Universal PCI Communication Card with Isolation & EFT Protection
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*