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參數(shù)資料
| 型號： | PCI6621 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DUAL/SINGLE SOCKET CARDBUS AND ULTRAMEDIA CONTROLLER |
| 中文描述： | 雙/單插槽CardBus和UltraMedia控制器 |
| 文件頁數(shù)： | 50/204頁 |
| 文件大?。?/td> | 860K |
| 代理商： | PCI6621 |
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32
3.2
I/O Characteristics
The PCI6x21/PCI6x11 controller meets the ac specifications of the
PC Card Standard
(release 8.1) and the
PCI Local
Bus Specification.
Figure 32 shows a 3-state bidirectional buffer. Section 10.2,
Recommended Operating
Conditions
, provides the electrical characteristics of the inputs and outputs.
Tied for Open Drain
OE
Pad
VCCP
Figure 32. 3-State Bidirectional Buffer
3.3
Clamping Voltages
The clamping voltages are set to match whatever external environment the PCI6x21/PCI6x11 controller is interfaced
with: 3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from
external signals. The core power supply is 1.5 V and is independent of the clamping voltages. For example, PCI
signaling can be either 3.3 V or 5 V, and the PCI6x21/PCI6x11 controller must reliably accommodate both voltage
levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage
applied. If a system designer desires a 5-V PCI bus, then V
CCP
can be connected to a 5-V power supply.
3.4
Peripheral Component Interconnect (PCI) Interface
The PCI6x21/PCI6x11 controller is fully compliant with the
PCI Local Bus Specification
. The PCI6x21/PCI6x11
controller provides all required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V
signaling environment by connecting the V
CCP
terminals to the desired voltage level. In addition to the mandatory
PCI signals, the PCI6x21/PCI6x11 controller provides the optional interrupt signals INTA, INTB, INTC, and INTD.
3.4.1
Device Resets
During the power-up sequence, GRST and PRST must be asserted. GRST can only be deasserted 100
μ
s after PCLK
is stable, and 2 ms after V
CC
is stable. PRST can be deasserted at the same time as GRST or any time thereafter.
3.4.2
Serial EEPROM I
2
C Bus
The PCI6x21/PCI6x11 controller offers many choices for modes of operation, and these choices are selected by
programming several configuration registers. For system board applications, these registers are normally
programmed through the BIOS routine. For add-in card and docking-station/port-replicator applications, the
PCI6x21/PCI6x11 controller provides a two-wire inter-integrated circuit (IIC or I
2
C) serial bus for use with an external
serial EEPROM.
The PCI6x21/PCI6x11 controller is always the bus master, and the EEPROM is always the slave. Either device can
drive the bus low, but neither device drives the bus high. The high level is achieved through the use of pullup resistors
on the SCL and SDA signal lines. The PCI6x21/PCI6x11 controller is always the source of the clock signal, SCL.
System designers who wish to load register values with a serial EEPROM must use pullup resistors on the SCL and
SDA terminals. If the PCI6x21/PCI6x11 controller detects a logic-high level on the SCL terminal at the end of GRST,
then it initiates incremental reads from the external EEPROM. Any size serial EEPROM up to the I
2
C limit of 16 Kbits
can be used, but only the first 96 bytes (from offset 00h to offset 5Fh) are required to configure the PCI6x21/PCI6x11
controller. Figure 33 shows a serial EEPROM application.
In addition to loading configuration data from an EEPROM, the PCI6x21/PCI6x11 I
2
C bus can be used to read and
write from other I
2
C serial devices. A system designer can control the I
2
C bus, using the PCI6x21/PCI6x11 controller
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