![](http://datasheet.mmic.net.cn/330000/PCI7610LQFP_datasheet_16443884/PCI7610LQFP_39.png)
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Table 215. CardBus PC Card Interface Control Terminals
TERMINAL
NAME
NUMBER
PDV
I/O
DESCRIPTION
GHK
CAUDIO
184
F10
I
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI7610
controller supports the binary audio mode and outputs a binary signal from the card to SPKROUT.
CBLOCK
153
E18
I/O
CardBus lock. CBLOCK is used to gain exclusive access to a target.
CCD1
CCD2
125
187
L17
C09
I
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and
CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type.
CDEVSEL
157
A16
I/O
CardBus device select. The PCI7610 controller asserts CDEVSEL to claim a CardBus cycle as the
target device. As a CardBus initiator on the bus, the PCI7610 controller monitors CDEVSEL until a
target responds. If no target responds before timeout occurs, then the PCI7610 controller terminates
the cycle with an initiator abort.
CFRAME
161
B15
I/O
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted
to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When CFRAME is deasserted, the CardBus bus transaction is in the final data phase.
CGNT
156
D19
O
CardBus bus grant. CGNT is driven by the PCI7610 controller to grant a CardBus PC Card access to
the CardBus bus after the current data transaction has been completed.
CINT
182
C10
I
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the
host.
CIRDY
160
F13
I/O
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and
CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.
CPERR
154
F15
I/O
CardBus parity error. CPERR reports parity errors during CardBus transactions, except during special
cycles. It is driven low by a target two clocks following the data cycle during which a parity error is
detected.
CREQ
173
B12
I
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus
bus as an initiator.
CSERR
183
E10
I
CardBus system error. CSERR reports address parity errors and other system errors that could lead
to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak
pullup; deassertion may take several CCLK periods. The PCI7610 controller can report CSERR to the
system by assertion of SERR on the PCI interface.
CSTOP
155
E17
I/O
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus
transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that
do not support burst data transfers.
CSTSCHG
185
A09
I
CardBus status change. CSTSCHG alerts the system to a change in the card status, and is used as
a wake-up mechanism.
CTRDY
159
E14
I/O
CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and
CTRDY are asserted; until this time, wait states are inserted.
CVS1
CVS2
181
167
B10
F12
I/O
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with
CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and
card type.