參數(shù)資料
型號(hào)： PCI7610LQFP
廠商： Texas Instruments, Inc.
英文描述： PC Card, UltraMedia, and Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller
中文描述： PC卡，UltraMedia和集成1394 - 2000 OHCI的雙端口的PHY /鏈路層控制器
文件頁(yè)數(shù)： 80/240頁(yè)
文件大小： 1298K
代理商： PCI7610LQFP
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44
4.5
Command Register
The PCI command register provides control over the PCI7610 interface to the PCI bus. All bit functions adhere to the
definitions in the
PCI Local Bus Specification
(see Table 43). None of the bit functions in this register are shared
among the PCI7610 PCI functions. Three command registers exist in the PCI7610 controller, one for each function.
Software manipulates the PCI7610 functions as separate entities when enabling functionality through the command
register. The SERR_EN and PERR_EN enable bits in this register are internally wired OR between the three
functions, and these control bits appear to software to be separate for each function.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Command
Type
R
R
R
R
R
RW
R
RW
R
RW
RW
R
R
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Command
04h
Read-only, Read/Write
0000h
Table 43. Command Register Description
BIT
SIGNAL
TYPE
FUNCTION
1511
RSVD
R
Reserved. Bits 1511 return 0s when read.
10
INT_DISABLE
RW
INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.
0 = INTx assertion is enabled (default)
1 = INTx assertion is disabled
This bit is disabled (read-only 0) if bit 7 (PCI2_3_EN) in the general control register (PCI offset 86h, see
Section 4.32) is 0.
9
FBB_EN
R
Fast back-to-back enable. The PCI7610 controller does not generate fast back-to-back transactions;
therefore, this bit is read-only. This bit returns a 0 when read.
8
SERR_EN
RW
System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR
can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set
for the PCI7610 controller to report address parity errors.
0 = Disables the SERR output driver (default)
1 = Enables the SERR output driver
7
RSVD
R
Reserved. Bit 7 returns 0 when read.
6
PERR_EN
RW
Parity error response enable. This bit controls the PCI7610 response to parity errors through the PERR
signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by
asserting SERR.
0 = PCI7610 controller ignores detected parity errors (default).
1 = PCI7610 controller responds to detected parity errors.
5
VGA_EN
RW
VGA palette snoop. When set to 1, palette snooping is enabled (i.e., the PCI7610 controller does not
respond to palette register writes and snoops the data). When the bit is 0, the PCI7610 controller treats
all palette accesses like all other accesses.
4
MWI_EN
R
Memory write-and-invalidate enable. This bit controls whether a PCI initiator device can generate memory
write-and-invalidate commands. The PCI7610 controller does not support memory write-and-invalidate
commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. This bit returns
0 when read. Writes to this bit have no effect.
3
SPECIAL
R
Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The PCI7610
controller does not respond to special cycle operations; therefore, this bit is hardwired to 0. This bit returns
0 when read. Writes to this bit have no effect.
2
MAST_EN
RW
Bus master control. This bit controls whether or not the PCI7610 controller can act as a PCI bus initiator
(master). The PCI7610 controller can take control of the PCI bus only when this bit is set.
0 = Disables the PCI7610 ability to generate PCI bus accesses (default)
1 = Enables the PCI7610 ability to generate PCI bus accesses
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