參數(shù)資料
型號(hào)： PCI7610LQFP
廠商： Texas Instruments, Inc.
英文描述： PC Card, UltraMedia, and Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller
中文描述： PC卡，UltraMedia和集成1394 - 2000 OHCI的雙端口的PHY /鏈路層控制器
文件頁(yè)數(shù)： 69/240頁(yè)
文件大?。?/td> 1298K
代理商： PCI7610LQFP
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327
NOTE 2: The PWR_STATE bits (bits 10) of the power-management control/status register (PCI offset A4h, see Section 4.45) only code for four
power states, D0, D1, D2, and D3hot. The differences between the three D3 states is invisible to the software because the controller
is not accessible in the D3cold or D3off state.
Similarly, bus power states of the PCI bus are B0B3. The bus power states B0B3 are derived from the device power
state of the originating bridge device.
For the operating system (OS) to manage the device power states on the PCI bus, the PCI function must support four
power-management operations. These operations are:
Capabilities reporting
Power status reporting
Setting the power state
System wake-up
The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of
capabilities in addition to the standard PCI capabilities is indicated by a 1 in bit 4 (CAPLIST) of the status register (PCI
offset 06h, see Section 4.6).
The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI7610 controller,
a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h.
The first byte of each capability register block is required to be a unique ID of that capability. PCI power management
has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there
are no more items in the list, then the next item pointer must be set to 0. The registers following the next item pointer
are specific to the capability of the function. The PCI power-management capability implements the register block
outlined in Table 317.
Table 317. Power-Management Registers
REGISTER NAME
OFFSET
Power-management capabilities
Next item pointer
Capability ID
A0h
Data
Power-management control/status register bridge support extensions
Power-management control/status (CSR)
A4h
The power-management capabilities register (PCI offset A2h, see Section 4.44) is a static read-only register that
provides information on the capabilities of the function related to power management. The power-management
control/status register (PCI offset A4h, see Section 4.45) enables control of power-management states and
enables/monitors power-management events. The data register is an optional register that can provide dynamic data.
For more information on PCI power management, see the
PCI Bus Power Management Interface Specification for
PCI to CardBus Bridges
.
3.9.9.1 Function 2 Power Management
The PCI7610 controller complies with the
PCI Bus Power Management Interface Specification
. The controller
supports the D0 (unitialized), D0 (active), D1, D2, and D3 power states as defined by the power management
definition in the
1394 Open Host Controller Interface Specification
, Appendix A4.
Table 318. Function 2 Power-Management Registers
REGISTER NAME
OFFSET
Power-management capabilities
Next item pointer
Capability ID
44h
Data
Power-management control/status register bridge support extensions
Power-management control/status (CSR)
48h
3.9.9.2 Function 3 Power Management
The
PCI Bus Power Management Interface Specification
is applicable for the firmware loader. This function supports
the D0 and D3 power states.
Table 319. Function 3 Power-Management Registers
REGISTER NAME
OFFSET
Power-management capabilities
Next item pointer
Capability ID
44h
Data
Power-management control/status register bridge support extensions
Power-management control/status (CSR)
48h
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