參數(shù)資料
型號(hào): PCM3060PWR
元件分類(lèi): Codec
英文描述: 24-BIT, 96/192-kHz ASYNCHRONOUS STEREO AUDIO CODEC
中文描述: 24位96/192-kHz異步立體聲音頻編解碼
文件頁(yè)數(shù): 19/45頁(yè)
文件大?。?/td> 394K
代理商: PCM3060PWR
www.ti.com
PCM AUDIO INTERFACE
Audio Interface Mode and Timing
DOUT
0.5 V
DD
1.4 V
1.4 V
DIN
1.4 V
BCK1/2
(Input)
LRCK1/2
(Input)
t
(BCY)
t
(DIH)
t
(BCH)
t
(BCL)
t
(LRS)
t
(DIS)
t
(DOD)
T0247-01
t
(LRH)
PCM3060
SLAS533–MARCH 2007
The digital audio data can be interfaced in either slave or master mode, and this interface mode is selectable
using the serial mode control described in the Mode Control section.
The interface mode is also selectable independently for the ADC and the DAC. DIN is always input to the
PCM3060 and DOUT is always an output from the PCM3060. Slave mode is the default mode for both the ADC
and the DAC.
In slave mode, BCK1/2 and LRCK1/2 are inputs to the PCM3060, and BCK1/2 must be either 64 f
S
or 48 f
S
. DIN
is sampled on the rising edge of BCK2, and DOUT is changed on the falling edge of BCK1. The default timing
specification is shown in
Figure 24
.
In master mode, BCK1/2 and LRCK1/2 are outputs from the PCM3060. BCK1/2 and LRCK1/2 are generated by
the PCM3060 from SCKI1/2, and BCK1/2 is fixed at 64 f
S
. DIN is sampled on the rising edge of BCK2, and
DOUT is changed on the falling edge of BCK1. The detailed timing specification is shown in
Figure 25
.
SYMBOL
t
(BCY)
t
w (BCH)
t
w (BCL)
t
(LRS)
t
(LRH)
t
(DIS)
t
(DIH)
t
(DOD)
DESCRIPTION
MIN
75
35
35
10
10
10
10
15
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
BCK1/2 cycle time
BCK1/2 high time
BCK1/2 low time
LRCK1/2 set-up time to BCK1/2 rising edge
LRCK1/2 hold time to BCK1/2 rising edge
DIN setup time to BCK1/2 rising edge
DIN hold time to BCK1/2 rising edge
DOUT delay time from BCK1/2 falling edge
70
NOTE: Load capacitance of output is 20 pF.
Figure 24. Audio Data Interface Timing (Slave Mode: BCK1/2 and LRCK1/2 Work as Inputs)
19
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