參數(shù)資料
型號(hào): PCM3060PWR
元件分類: Codec
英文描述: 24-BIT, 96/192-kHz ASYNCHRONOUS STEREO AUDIO CODEC
中文描述: 24位96/192-kHz異步立體聲音頻編解碼
文件頁(yè)數(shù): 28/45頁(yè)
文件大?。?/td> 394K
代理商: PCM3060PWR
www.ti.com
Timing Diagram
SDA
SCL
t
(BUF)
t
(D-SU)
t
(D-HD)
Start
t
(LOW)
t
(S-HD)
t
(SCL-F)
t
(SCL-R)
t
(HI)
Repeated Start
t
(S-SU)
t
(S-HD)
t
(SDA-F)
t
(P-SU)
t
(SDA-R)
Stop
t
(GW)
T0050-04
PCM3060
SLAS533–MARCH 2007
The detailed timing diagram for SCL and SDA is shown as follows.
Timing Characteristics
STANDARD MODE
FAST MODE
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX
f
(SCL)
t
(BUF)
t
(LOW)
t
(HI)
t
(S-SU)
t
(S-HD)
t
(D-SU)
t
(D-HD)
t
(SCL-R)
t
(SCL-F)
t
(SDA-R)
t
(SDA-F)
t
(P-SU)
t
(GW)
C
B
SCL clock frequency
100
400
kHz
Bus free time between STOP and START conditions
4.7
1.3
μ
s
μ
s
μ
s
μ
s
μ
s
ns
Low period of the SCL clock
4.7
1.3
High period of the SCL clock
4
0.6
Setup time for START/repeated START condition
4.7
0.6
Hold time for START/repeated START condition
4
0.6
Data setup time
250
100
Data hold time
0
3450
0
900
ns
Rise time of SCL signal
1000
20 + 0.1 C
B
20 + 0.1 C
B
20 + 0.1 C
B
20 + 0.1 C
B
0.6
300
ns
Fall time of SCL signal
1000
300
ns
Rise time of SDA signal
1000
300
ns
Fall time of SDA signal
1000
300
ns
Setup time for STOP condition
4
μ
s
ns
Allowable glitch width
N/A
50
Capacitive load for SDA and SCL lines
400
100
pF
Noise margin at high level for each connected device (including hysteresis)
0.2 V
DD
0.1 V
DD
N/A
0.2 V
DD
0.1 V
DD
0.05 V
DD
V
Noise margin at low level for each connected device (including hysteresis)
V
Hysteresis of Schmitt-trigger input
V
Figure 32. Control Interface Timing for I
2
C
28
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