參數(shù)資料
型號(hào): PEB2466-HV1.2
廠商: SIEMENS A G
元件分類: 編解碼器
英文描述: Four Channel Codec Filter with PCM- and m-Controller Interface SICOFI4-mC
中文描述: A/MU-LAW, PCM CODEC, PQFP64
文件頁(yè)數(shù): 10/82頁(yè)
文件大?。?/td> 3330K
代理商: PEB2466-HV1.2
PEB 2466
General Description
Semiconductor Group
10
02.97
1.3
Pin Definition and Functions
Pin No. Symbol
Input (I)
Output (O)
Function
Common Pins for all Channels
24
21
V
DDD
GNDD
I
I
+ 5 V supply for the digital circuitry
1)
Ground Digital, not internally connected to
GNDA1,2,3,4
All digital signals are referred to this pin
+ 5 V Analog supply voltage for channel 1 and 2
1)
+ 5 V Analog supply voltage for channel 3 and 4
1)
Reference voltage, has to be connected to a 220 nF
cap. to ground, can also be used as virtual ground
for analog inputs and outputs (high-ohmic buffer
needed !!!)
+ 5 V Analog supply voltage (100 nF cap. required)
Frame synchronization clock, 8 kHz, identifies the
beginning of the frame, individual time slots are
referenced to this pin, FSC must be synchronous to
PCLK
Data clock 128 to 8192 kHz, determines the rate at
which PCM data is shifted into or out of the
PCM-ports
PCM-interface: Receive PCM data from
PCM-highway B, data for each channel is received
in 8 bit bursts every 125
μ
s
PCM-interface: Transmit PCM data to PCM-highway
B, data for each channel is transmitted in 8 bit burst
every 125
μ
s
PCM-interface: Transmit control output B, is active if
data is transmitted via DXB, active low, open drain
PCM-interface: Receive PCM data from
PCM-highway A, data for each channel is received
in 8 bit bursts every 125
μ
s
PCM-interface: Transmit PCM data to PCM-highway
A, data for each channel is transmitted in 8 bit burst
every 125
μ
s
52
61
56
V
DDA12
V
DDA34
V
REF
I
I
I/O
57
31
V
DDREF
FSC
I
I
32
PCLK
I
30
DRB
I
29
DXB
O
28
TCB
O
27
DRA
I
26
DXA
O
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