參數(shù)資料
型號: PEB2466-HV1.2
廠商: SIEMENS A G
元件分類: 編解碼器
英文描述: Four Channel Codec Filter with PCM- and m-Controller Interface SICOFI4-mC
中文描述: A/MU-LAW, PCM CODEC, PQFP64
文件頁數(shù): 36/82頁
文件大小: 3330K
代理商: PEB2466-HV1.2
PEB 2466
Programming the SICOFI
-4-
μ
C
Semiconductor Group
36
02.97
3.3.4
CR3 Configuration Register 3
1)
In this case the transmit-path signal is attenuated 0.06 dB
In this case the receive-path signal is attenuated 0.12 dB
2)
Bit 7
0
Test-Loops
AGX
AGR
D-HPX
D-HPR
Test-Loops
4 bit field for selection of Analog and Digital Loop Backs
0 0 0 0:
0 0 0 1:
ALB-PFI
0 0 1 1:
ALB-4M
0 1 0 0:
ALB-PCM
No loop back is selected (normal operation)
Analog loop back via PREFI-POFI is selected
Analog loop back via 4 MHz is selected
Analog loop back via 8 kHz (PCM) is selected
(attention: special settings necessary)
Analog loop back via 8 kHz (linear) is selected
Digital loop back via analog port is selected
Digital loop back via 4 MHz is selected
Digital loop back via 128 kHz is selected
Digital loop back via 64 kHz is selected
Digital loop back via PCM-registers is selected
0 1 0 1:
1 0 0 0:
1 0 0 1:
1 1 0 0:
1 1 0 1:
1 1 1 1:
ALB-8K
DLB-ANA
DLB-4M
DLB-128K
DLB-64K
DLB-PCM
AGX
Analog gain in transmit direction
AGX = 0:
Analog gain is disabled
AGX = 1:
Analog gain is enabled (6.02 dB amplification)
AGR
Analog gain in receive direction
AGR = 0:
Analog gain is disabled
AGR = 1:
Analog gain is enabled (6.02 dB attenuation)
D-HPX
Disable highpass in transmit direction
D-HPX = 0:
Transmit high pass is enabled
D-HPX = 1:
Transmit high pass is disabled
1)
D-HPR
Disable highpass in receive direction
D-HPR = 0:
Receive high pass is enabled
D-HPR = 1:
Receive high pass is disabled
2)
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