參數(shù)資料
型號: PEB24902
廠商: SIEMENS A G
元件分類: 數(shù)字傳輸電路
英文描述: Quad ISDN Echocancellation Circuit Analogue Front End Quad IEC AFE
中文描述: DATACOM, ISDN ECHO CANCELLER, PQFP64
文件頁數(shù): 19/50頁
文件大?。?/td> 502K
代理商: PEB24902
PEB 24902
PEF 24902
Technical Description
Semiconductor Group
19
05.96
3
Technical Description
3.1
All timing signals are derived from a 15.36 MHz system clock. The 15.36 MHz clock can
be provided by the Quad IEC AFE by a crystal-based PLL, which is synchronized to
either an 8 kHz or a 2048 kHz clock at pin CLOCK. The frequency at pin CLOCK is
detected automatically.
The 15.36 MHz clock can also be provided externally at pin CL15 without making use of
the internal PLL. In this mode the pin XIN must be tied to either VDD or GND. An internal
power-on-reset circuitry assures that the pin CL15 is an input until a 15.36 MHz clock is
detected at the output of the PLL/oscillator.
Clock Generation
3.1.1
The PLL is based on a crystal connected to the pins XIN and XOUT. For synchronization
of the 15.36 MHz clock up to 16 internal capacitances are connected to XIN and XOUT.
The loop filter of the PLL is of second order, therefore a sinusoidal input jitter with the
angular frequency
ω
= 2
π
f
at CLOCK is amplified by the PLL according to the following
formula:
Specification of the PLL and the 15.36 MHz Master Clock (Pin CL15)
H(j
ω
) is the complex jitter transfer factor
ω
r
= 2
π
f
r
is the angular resonance-frequency of the PLL
δ
is the damping factor of the PLL
The maximum phase difference between the external CLOCK and the internal
reference, derived from the master clock, due to a sinusoidal input jitter with the angular
frequency
ω
is given as 1 - H(j
ω
). The magnitude of the jitter transfer function and of the
phase difference are illustrated below:
H j
ω
)
2
δ
ω
r
2
-----j
ω
1
+
j
ω
ω
r
-----
2
δ
ω
r
-----j
ω
1
+
+
-----------------------------------------
=
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