參數(shù)資料
型號: PEB24902
廠商: SIEMENS A G
元件分類: 數(shù)字傳輸電路
英文描述: Quad ISDN Echocancellation Circuit Analogue Front End Quad IEC AFE
中文描述: DATACOM, ISDN ECHO CANCELLER, PQFP64
文件頁數(shù): 22/50頁
文件大?。?/td> 502K
代理商: PEB24902
PEB 24902
PEF 24902
Technical Description
Semiconductor Group
22
05.96
3.1.2
A crystal (serial resonance) has to be connected to XIN and XOUT which shall meet the
following specification:
Specification of the Crystal
Start-up time of the Oscillator
with the crystal suggested
below.
Input capacitance at XIN and
XOUT
Output current at XOUT during
start-up
Output current at XOUT after
synchronization
0.5
1
ms
3
15
pF
0.5
1
mA
0.5
1
mA
Table 3
PLL Input Requirements
Parameter
Limit Values
typ.
0
Unit
min.
-150
max.
+150
Accuracy of the reference at
CLOCK to enable
synchronization
Peak-to peak Jitter of the
CLOCK signal during any 125
μsec period
Peak-to-peak voltage of a
sinusoidal external master clock
provided at XIN
Low time of the reference at
CLOCK
High time of the reference at
CLOCK
Pulse width of the 15MHz clock
ppm
70
ns
3.3
V
pp
130
ns
130
ns
26
39
ns
Table 2
PLL Characteristcs
(cont’d)
Parameter
Limit Values
typ.
Unit
min.
max.
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