參數(shù)資料
型號(hào)： PEF20324
廠商： INFINEON TECHNOLOGIES AG
英文描述： ICs for Communications
中文描述： 通信集成電路
文件頁(yè)數(shù)： 17/63頁(yè)
文件大?。?/td> 705K
代理商： PEF20324
PEB 20324
PEF 20324
Pin Descriptions
Hardware Reference Manual
17
04.99
Table 2-1
Pin No.
114
Pin Descriptions by Functional Block: Port 0 Serial Interface
Symbol
Type Description
RxCLK0
I
Receive Clock 0
The clock input pin used for sampling the data on
RxD0. The MUNICH128X supports the following PCM
clock rates; programmed via the MODE1 register:
T1: 1.536 MHz, 1.544 MHz, 3.088 MHz, 6.176 MHz;
E1: 2.048 MHz, 4.096 MHz, 8.192 MHz.
RxD0
I
Receive Data 0
The data input pin which is sampled using RxCLK0.
RSP0
I
Receive Synchronization Pulse 0
The input pin used for Rx PCM frame synchronization;
the synchronization pulse marks the firstbit in the
PCM frame.
TxCLK0
I
Transmit Clock 0
The clock input used for clocking out the data on
TxD0. In most applications, the signal that drives this
pin is externally connected to RxCLK0.
TxD0
O
Transmit Data 0
Provides the data which is clocked out of the
MUNICH128X by TxCLK0; data is push-pull for active
bits in the PCM frame and TRISTATE
for inactive
bits.
TSP0
I
Transmit Synchronization Pulse 0
The input pin used for Tx PCM frame synchronization;
the synchronization pulse marks the lastbit in the
PCM frame.
TxDEN0
O
Transmit Data Enable 0
An active low output signal which specifies data on the
TxD0 output pin is valid.
112
113
108
110
109
111
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