參數(shù)資料
型號(hào)： PEF20324
廠商： INFINEON TECHNOLOGIES AG
英文描述： ICs for Communications
中文描述： 通信集成電路
文件頁(yè)數(shù)： 47/63頁(yè)
文件大小： 705K
代理商： PEF20324
PEB 20324
PEF 20324
Electrical Characteristics
Hardware Reference Manual
47
04.99
5.7.1.2
The transaction starts when FRAME is activated (clock 2 in
figure 5-5
). A write
transaction is similar to a read transaction except no turnaround cycle is required
following the address phase. In the example, the first and second data phases complete
with zero wait cycles. The third data phase has three wait cycles inserted by the target.
Both initiator and target insert a wait cycle on clock 5. In the case where the initiator
inserts a wait cycle (clock 5), the data is held on the bus, but the byte enables are
withdrawn. The last data phase is characterized by IRDY being asserted while the
FRAME signal is deasserted. This data phase is completed when TRDY goes active
(clock 8).
PCI Write Transaction
Figure 5-5
PCI Write Transaction
ITD07576
Address
1
2
3
4
5
6
7
8
9
Bus CMD
W
CLK
FRAME
AD
C/BE
IRDY
TRDY
DEVSEL
Address
Phase
Data
Phase
Bus Transaction
BE’s-1
D
D
D
W
W
Data 1
Data 2
Data 3
BE’s-2
BE’s-3
Phase
Data
Data
Phase
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