參數(shù)資料
型號: PEF20324
廠商: INFINEON TECHNOLOGIES AG
英文描述: ICs for Communications
中文描述: 通信集成電路
文件頁數(shù): 32/63頁
文件大?。?/td> 705K
代理商: PEF20324
PEB 20324
PEF 20324
Functional Description
Hardware Reference Manual
32
04.99
3.3.3.3
This block controls memory address calculation, buffer management (including linked-
lists) and interrupt processing. The 24/32-channel HDLC Controller has a dedicated
DMA channel for each channel and direction. During run-time, the DMA Controller
performs operations with host memory primarily as a bus master. This block provides
32 input and 32 output channels.
64-channel DMA Controller Block
3.3.3.4
This block provides configuration and control of the Serial PCM Interface Controller, the
HDLC Controller and the DMA Controller. Also, a shared status register STAT provides
status and interrupt information associated with each of the four cores.
Register Set
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