參數(shù)資料
型號(hào)： PEF20324
廠商： INFINEON TECHNOLOGIES AG
英文描述： ICs for Communications
中文描述： 通信集成電路
文件頁(yè)數(shù)： 6/63頁(yè)
文件大?。?/td> 705K
代理商： PEF20324
PEB 20324
PEF 20324
List of Tables
Page
Hardware Reference Manual
6
04.99
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Pin Descriptions by Functional Block: Port 0 Serial Interface. . . . . . . 17
Pin Descriptions by Functional Block: Port 1 Serial Interface . . . . . . . 18
Pin Descriptions by Functional Block: Port 2 Serial Interface . . . . . . . 19
Pin Descriptions by Functional Block: Port 3 Serial Interface . . . . . . . 20
Pin Descriptions by Functional Block: PCI Interface . . . . . . . . . . . . . . 21
Pin Descriptions by Functional Block:
DEMUX Interface (additional signals to PCI Interface) . . . . . . . . . . . . 25
Pin Descriptions by Functional Block: Power Supply. . . . . . . . . . . . . . 26
Pin Descriptions by Functional Block: Test Interface. . . . . . . . . . . . . . 27
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Non-PCI Interface Pins
TA = 0 to + 70
×C; VDD5 = 5 V
±
5%, VDD3 = 3.3 V
±
0.3 V,
VSS = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Non-PCI Interface Pins
TA = 25×C; VDD5 = 5 V
±
5%, VDD3 = 3.3 V
±
0.3 V, VSS = 0 V . . . 42
PCI Input and Output Measurement Conditions . . . . . . . . . . . . . . . . . 44
Number of Wait States Inserted by the MUNICH128X as Initiator. . . . 48
Number of Wait States Inserted by the MUNICH128X as Slave . . . . . 48
PCI Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PCI Interface Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Additional De-multiplexed Interface Signal Characteristics . . . . . . . . . 52
PCM Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
System Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Boundary Scan Sequence in MUNICH128X . . . . . . . . . . . . . . . . . . . . 58
Boundary Scan Test Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 2-7
Table 2-8
Table 5-1
Table 5-2
Table 5-3
Table 5-4
Table 5-5
Table 5-6
Table 5-7
Table 5-8
Table 5-9
Table 5-10
Table 5-11
Table 5-12
Table 5-13
Table 6-1
Table 6-2
相關(guān)PDF資料
PDF描述
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