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參數(shù)資料
| 型號(hào)： | PEF2080 |
| 廠商： | SIEMENS AG |
| 英文描述： | S/T Bus Interface Circuit(SBC) |
| 中文描述： | S / T的總線接口電路（SBC）的 |
| 文件頁數(shù)： | 59/74頁 |
| 文件大?。?/td> | 2620K |
| 代理商： | PEF2080 |
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Semiconductor Group
60
Electrical Characteristics
AC Characteristics
T
A
= 0 to 70 C,
V
DD
= 5 V
±
5 % for PEB 2080
T
A
= – 40 to 85 C,
V
DD
= 5 V
±
5 % for PEF 2080
The AC testing input/output waveform is shown below.
Figure 32
Input / Output Waveform for AC Test
Jitter
In TE mode, the timing extraction jitter of the SBC conforms to CCITT Recommendation I.430
(– 7 % to + 7 % of the S-interface bit period). In the NT and LT-S applications, the clock input DCL
is used as reference clock to provide the 192-kHz clock for the S line interface. In the case of a
plesiochronous 7.68-MHz clock generated by an oscillator, the clock DCL should have a jitter of less
than 100 ns peak-to-peak. (In the case of a zero input jitter on DCL, SBC generates at most 130 ns
“self-jitter” on S interface.) In the case of a synchronous (fixed divider ratio of 15 between XTAL1
and DCL) 7.68-MHZ clock (input XTAL1), the SBC transfers the input jitter of XTAL1, DCL and FSC
to the S interface. The maximum jitter of the NT/LT-S output is limited to 260 ns peak-to-peak
(CCITT I.430).
Clock Timing
The clocks in the different operating modes are summarized in
table 7
, with duty ratios. Clock CP
is phase-locked to the receive S signal, and is derived using the internal DPLL and the
7.68 MHz
±
100 ppm crystal (TE and LT-T). A phase tracking of CP with respect to “S” is performed
once in 250
μ
s. As a consequence of this DPLL tracking, the high state of CP may be either reduced
or extended by one 7.68 MHz period (CP duty ratio 2:2 or 4:2 instead of 3:2) once every 250
μ
s.
Since DCL and FSC are derived from CP (TE mode), the high state (FSC) or the high or low state
(DCL) may likewise be reduced or extended by the same amount once every 250
μ
s. (The phase
adjustment may take place either in the sixth, seventh or eighth CP cycle counting from the
beginning of an IOM frame in TE).
The phase relationships of the auxiliary clocks are shown in
figure 29
.
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