參數(shù)資料
型號(hào)： pentium pro processor
廠商： Intel Corp.
英文描述： Pentium Pro Processor with 1MB L2 Cache at 200MHZ(1兆比特L2高速緩存頻率200兆赫茲處理器)
中文描述： 奔騰Pro處理器在200MHz（1兆比特二級(jí)高速緩存頻率200兆赫茲處理器帶有1MB的L2緩存）
文件頁(yè)數(shù)： 25/39頁(yè)
文件大小： 930K
代理商： PENTIUM PRO PROCESSOR
E
AP-523
25
point should also be wide, even though the current is
low, in order to keep its inductance minimal.
If one source of the V
TT
voltage is used to power both
ends of the bus, and the ends are not near each other,
then a plane may be useful for V
TT
distribution. This will
help offset the resistive and inductive losses that are an
issue for V
TT
distribution just as they are issues for
V
CC
P. Separate smaller linear regulators at each end of
the bus may alleviate the possible need for a power
plane.
NOTE
When using resistor networks with single corner
pin V
connections for GTL+ termination,
beware of inductive packages. Intel has found
that these packages can cause significant voltage
drops due to the inductance in the 24 pin SOIC
packages being used for this purpose.
6.3.
Generating and Distributing
V
REF
V
REF
is a low current input to the differential receivers
within each of the components on the GTL+ bus. As it is
fairly low current (at most 15
m
A per device), it can be
generated by a simple voltage divider. Because V
REF
is
used only by the input buffers, it does not need to
maintain a tight tolerance from component to component.
It does however need to meet the 2% specification at all
V
REF
inputs and should track the V
TT
averaging that
occurs if using two regulators at opposite ends of the bus.
The V
REF
specification is 2/3 V
TT
±
2%. By using 1%
resistors one can easily meet this specification. In
Figure 22, using R
1
= 2
′
R
2
, V
REF
is set at a nominal
value of 2/3 V
TT
.
Equation 11. Creating V
REF
of 2/3 V
TT
V
V
R
+
R
R
V
R
+
R
R
V
REF
TT
TT
TT
=
×
=
×
×
×
=
1
1
2
2
2
2
23
2
2
R
1
and R
2
should be small enough values that the current
drawn by the V
REF
inputs (I
REF
) is negligible versus the
current caused by R
2
and R
1
.
A complete analysis of this circuit’s currents into and out
of the center node, as in Equation 12, will provide the
final V
REF
of the circuit.
n
is the number of I
REF
inputs
supplied by the divider.
R
2
V
V
TT
R
1
V
REF
I
S
I
REF
SS
Figure 22. V
REF
Equation 12. Node Analysis
I R
I R
n
I
)
)
2
1
=
+
×
REF
Plugging in for the currents and rearranging, gives:
Equation 13. Node Analysis in Terms of Voltage
V
V
R
V
R
n
I
TT
REF
REF
REF
=
×
2
1
Which leads to:
Equation 14. Solving for V
REF
V
V
R
n
I
R
R
REF
TT
REF
=
+
×
2
2
1
1
1
The worst case V
REF
should be analyzed with I
REF
at the
maximum and minimum values determined for the
number of loads being provided voltage. If the number of
loads can change from model to model or because of
upgrades, this should be taken into account as well.
Equation 14 should also be analyzed with R
1
and R
2
at
the extremes of their tolerance specifications.
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