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| 型號(hào)： | pentium pro processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium Pro Processor with 1MB L2 Cache at 200MHZ(1兆比特L2高速緩存頻率200兆赫茲處理器) |
| 中文描述： | 奔騰Pro處理器在200MHz（1兆比特二級(jí)高速緩存頻率200兆赫茲處理器帶有1MB的L2緩存） |
| 文件頁(yè)數(shù)： | 26/39頁(yè) |
| 文件大?。?/td> | 930K |
| 代理商： | PENTIUM PRO PROCESSOR |
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AP-523
E
26
6.3.1.
DISTRIBUTING V
REF
OR V
TT
A resistor divider can be placed at each component by
distributing V
TT
, or V
REF
can be generated at a voltage
regulator and then distributed to each of the devices. To
eliminate noise and losses on whichever level is
distributed, use a wide isolated trace. The current should
be fairly low in either case, but this extra width will help
keep the induced noise level down.
If more than one regulator is being used to generate V
TT
,
then V
REF
must track them by averaging from both V
TT
sources. One method of accomplishing this is to generate
a separate V
REF
at each regulator for up to four loads
each, and then connect the two together with a wide
trace. The closer this V
REF
signal tracks the path of the
bus signals, the better it will match the averaging of the
voltage on the GTL+ bus. However, this signal should be
routed on a separate layer in order to keep cross-talk off
of it.
7.0.
RECOMMENDATIONS
Designing and verifying one’s own system using
simulation is highly recommended. With the above
estimates, a model of the power source, and the provided
model of the Pentium Pro processor in Section 11, analog
modeling can be started. Intel recommends the following
as a starting point, or benchmark.
7.1.
V
CC
S
For V
CC
S, use a standard PC power supply with a 3.3V
tap. Be sure that there is sufficient current on the 3.3V
tap of the supply to power all of the system chipset, the
GTL+ regulator (if run off of 3.3V), other 3.3V logic in
the system and any possible L2 caches that may someday
exist in the system. See the chipset specification for
chipset
power
requirements.
motherboard
specifications in the
Pentium
a
Pro
Processor Developer’s Manual, Volume 1
for the
requirements of the L2 cache. Bulk decoupling
requirements will be highly dependent on the reaction
time of the power supply that is chosen. For high
frequency decoupling, twenty (20) 0.1
m
F capacitors in a
1206 package should be more than adequate. This should
limit di/dt noise to 20 mV. While this sounds
extravagant, it is wise to keep L2 noise isolated from
other components that will be sharing the 3.3V supply,
and vice versa. Note that no decoupling is required when
supporting only processors in which the L2 receives
power from the V
CC
P pins.
See
the
flexible
7.2.
V
CC
P
--
Figure 23. Local Regulation
For V
CC
P, Intel recommends starting with a socketed
local DC-to-DC converter as shown in Figure 23. This
removes cable inductance from the distribution, reduces
board inductance, and allows for a low cost upgrade
strategy as well. Regulator sockets can be provided for
upgradable processor sockets rather than shipping with
the full current capability already available. Another
benefit of using separate regulators per processor is the
ability to mix and match processor types in the system.
The output of this regulator should be adjustable to allow
for changes in the voltage specification as new products
become available.
Section 10 discusses recommended specifications for the
DC-to-DC converter. These specifications have been
provided to the DC-to-DC converter industry.
Intel recommends that the bulk decoupling be placed on
this DC-to-DC converter module. Since these capacitors
tend to be large and not available in surface mount
technology, it makes sense to isolate these to a smaller
module that can be run in a different manufacturing
environment than the typical system board designs. Up to
fourteen (14) 1000
m
F Electrolytic capacitors with an
ESR of less than 55 m
W
each should be placed
on the
converter module
, depending on the switching rate of
the converter.
The high frequency decoupling should be composed of
at least forty (40) 1.0
m
F capacitors in the 1206 package.
Ten or more are needed to meet the inductance
requirements and 40
m
F is required to slow the di/dt to
30A/
m
s for the DC-to-DC converter specification. These
should be placed close to the V
CC
P pins as shown in
Figure 20. An open centered socket will make this job
easier and allow for the use of the space immediately
under the processor. The plane can be constructed as an
island as in Figure 20 without any special isolation from
the signal layers.
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