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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 12/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
B-4
12/19/01 Revision 1.05
Frequently Asked Questions
1. What is the function of SCAN_EN?
SCAN_EN is for a full scan test or S_CLKIN select. During SCAN mode, SCAN_EN will be
driven to logic “0” or “l(fā)ogic “1” depending on functionality. During normal mode, if SCAN_EN
is connected to logic “0” (JP7 in the 1-2 position), S_CLKIN will be used for PLL test only
when PL_TM is active.
2. What is the function of SCAN_TM#?
SCAN_TM# is for full scan test and power on reset for the PLL. SCAN_TM# should be
connected to logic “1” or to an RC path (R1 and C13) during normal operation.
3. How do you use the external arbiter?
a) Disable the on chip arbiter by connecting S_CFN to logic “1” (JP4 in the 2-3 position).
b) Use S1_REQ#[0] as GRANT and S1_GNT#[0] as REQUEST on the S1 bus.
c) Use S2_REQ#[0] as GRANT and S2_GNT#[0] as REQUEST on the S2 bus.
4. What is the purpose of having JP1, JP2, and JP3?
JP1, JP2, and JP3 are designed for easy access to the primary bus signals. You may connect
any of these pins to an oscilloscope or a logic analyzer for observation. No connection is
required for normal operation. The following table indicates which bus signals correspond to
which pins.
1
2
3
4
5
6
7
8
9
1011
1213
14
15
16
JP2
REQ
AD29
AD26
CBE3
AD21
CBE2
IRDY
LOCK
PAR
AD14
AD11
CBE0
AD6
AD5
AD0
JP3
AD31
AD28
AD25
AD23
AD20
FRAM
E
DVSEL
PER
R
CBE1
AD13
AD10
AD8
AD4
AD2
GN
D
JP1
GNT
AD30
AD27
AD24
AD22
AD24
IRDY
STOP
SER
R
AD15
AD12
AD9
AD7
AD3
AD1
5. What is the purpose for having U17, U19, and U20?
U17, U19, and U20 are designed for easy access to the digital ground planes for observation.
6. How is the evaluation board constructed?
The evaluation board is a six-layer PCB. The top and bottom layers (1 and 6) are for signals,
power, and ground routing. Layer 2 and layer 5 are ground planes. Layer 3 is a digital 3.3V
power plane. Layer 4 is a digital 5V power plane with an island of analog 3.3V power.
7. What is the function of S_CLKIN?
The S_CLKIN pin is a test pin for the on chip PLL when PLL_TM is set to logic “1”.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8140AMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
| PI7C8140AMAE | 功能描述:外圍驅動器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
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