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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 49/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
25
06/04/02 Revision 1.07
abort condition, PI7C7300 responds with TRDY# to the next attempt of the con-
figuration transaction from the initiator. If more than one data transfer is requested,
PI7C7300 responds with a target disconnect operation during the first data phase.
4.9
Transaction Termination
This section describes how PI7C7300 returns transaction termination conditions back
to the initiator.
The initiator can terminate transactions with one of the following types of termination:
§
Normal termination
Normal termination occurs when the initiator de-asserts FRAME# at the beginning
of the last data phase, and de-asserts IRDY# at the end of the last data phase in
conjunction with either TRDY# or STOP# assertion from the target.
§
Master abort
A master abort occurs when no target response is detected. When the initiator does
not detect a DEVSEL# from the target within five clock cycles after asserting FRAME#,
the
initiator
terminates
the
transaction
with
a
master
abort.
If FRAME# is still asserted, the initiator de-asserts FRAME# on the next cycle, and
then de-asserts IRDY# on the following cycle. IRDY# must be asserted in the same
cycle in which FRAME# de-asserts. If FRAME# is already de-asserted, IRDY# can be
de-asserted on the next clock cycle following detection of the master abort condition.
The target can terminate transactions with one of the following types of termination:
§
Normal termination
TRDY# and DEVSEL# asserted in conjunction with FRAME# de-asserted and IRDY#
asserted.
§
Target retry
STOP# and DEVSEL# asserted with TRDY# de-asserted during the first data phase.
No data transfers occur during the transaction. This transaction must be repeated.
§
Target disconnect with data transfer
STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of
the transaction.
§
Target disconnect without data transfer
STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers
have been made. Indicates that no more data transfers will be made during this
transaction.
§
Target abort
STOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will
never be able to complete this transaction. DEVSEL# must be asserted for at least one
cycle during the transaction before the target abort is signaled.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8140AMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
| PI7C8140AMAE | 功能描述:外圍驅動器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
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