參數(shù)資料
型號: PI7C7300NA
廠商: PERICOM SEMICONDUCTOR CORP
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA272
封裝: PLASTIC, BGA-272
文件頁數(shù): 5/119頁
文件大小: 880K
代理商: PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
92
06/04/02 Revision 1.07
S1_DEVSEL#,
S2_DEVSEL#,
S1_STOP#,
S2_STOP#,
S1_LOCK#,
S2_LOCK#,
S1_PERR#, S2_PERR#, S1_SERR#, S2_SERR#, S1_REQ[7:0]#, S2_REQ[6:0]#,
S1_GNT[7:0]#, S2_GNT[6:0], S1_RESET#, S2_RESET#, S1_EN, S2_EN, HSLED,
HS_SW#, HS_EN, ENUM#.
17.3
3.3V AC Specifications
Figure 17-1. PCI Signal Timing Measurement Conditions
66 MHz
33 MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
Tsu
Input setup time to CLK – bused signals
1,2,3
3-
7
-
Tsu(ptp)
Input setup time to CLK – point-to-point
1,2,3
5
-
10, 12
4
-
Th
Input signal hold time from CLK
1,2
0-
0
-
Tval
CLK to signal valid delay – bused signals
1,2,3
26
2
11
Tval(ptp)
CLK to signal valid delay – point-to-point
1,2,3
26
2
12
Ton
Float to active delay
1,2
2-
2
-
Toff
Active to float delay
1,2
-14
-
28
ns
1. See Figure 16-1 PCI Signal Timing Measurement Conditions.
2. All primary interface signals are synchronized to P_CLK. All secondary interface
signals are synchronized to either S1_CLKOUT or S2_CLKOUT.
3. Point-to-point signals are P_REQ#, S1_REQ#[7:0], S2_REQ#[6:0], P_GNT#,
S1_GNT#[7:0], S2_GNT#[6:0], HSLED, HS_SW#, HS_EN, and ENUM#. Bused
signals are P_AD, P_BDE#, P_PAR, P_PERR#, P_SERR#, P_FRAME#,
P_IRDY#, P_TRDY#, P_LOCK#, P_DEVSEL#, P_STOP#, P_IDSEL, S1_AD,
S1_CBE#,
S1_PAR,
S1_PERR#,
S1_SERR#,
S1_FRAME#,
S1_IRDY#,
S1_TRDY#, S1_LOCK#, S1_devsel#, S1_STOP#, S2_AD, S2_CBE#, S2_PAR,
S2_PERR#, S2_SERR#, S2_FRAME#, S2_IRDY#, S2_TRDY#, S2_LOCK#,
S2_DEVSEL#, and S2_STOP#.
4. REQ# signals have a setup of 10 and GNT# signals have a setup of 12.
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