TM Family Datasheet Page 6 of 81 June 2009 – R" />
參數(shù)資料
型號： PI7C9X20505GPBNDE
廠商： Pericom
文件頁數(shù)： 56/81頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 256BGA
產(chǎn)品變化通告： Copper Wire Change 26/Sept/2011
標準包裝： 90
系列： GreenPacket™
應用： 封裝開關(guān)，5 端口/5 線道
接口： PCI Express
封裝/外殼： 256-BGA
供應商設(shè)備封裝： 256-PBGA（17x17）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20505GP
5Port-5Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 6 of 81
June 2009 – Revision 1.5
Pericom Semiconductor
7.2.7
CACHE LINE REGISTER – OFFSET 0Ch......................................................................................... 37
7.2.8
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ................................................................ 37
7.2.9
HEADER TYPE REGISTER – OFFSET 0Ch...................................................................................... 37
7.2.10
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ...................................................................... 37
7.2.11
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ................................................................ 37
7.2.12
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ............................................................ 37
7.2.13
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ........................................................... 37
7.2.14
I/O BASE ADDRESS REGISTER – OFFSET 1Ch.............................................................................. 38
7.2.15
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch............................................................................. 38
7.2.16
SECONDARY STATUS REGISTER – OFFSET 1Ch .......................................................................... 38
7.2.17
MEMORY BASE ADDRESS REGISTER – OFFSET 20h ................................................................... 39
7.2.18
MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h .................................................................. 39
7.2.19
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ..................................... 39
7.2.20
PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h.................................... 39
7.2.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h ......... 40
7.2.22
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch ....... 40
7.2.23
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h................................................... 40
7.2.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h.................................................. 40
7.2.25
CAPABILITY POINTER REGISTER – OFFSET 34h ......................................................................... 40
7.2.26
INTERRUPT LINE REGISTER – OFFSET 3Ch................................................................................. 40
7.2.27
INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................................... 41
7.2.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch .............................................................................. 41
7.2.29
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h ........................................... 42
7.2.30
NEXT ITEM POINTER REGISTER – OFFSET 80h........................................................................... 42
7.2.31
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h............................................. 42
7.2.32
POWER MANAGEMENT DATA REGISTER – OFFSET 84h ............................................................ 42
7.2.33
PPB SUPPORT EXTENSIONS – OFFSET 84h.................................................................................. 43
7.2.34
DATA REGISTER – OFFSET 84h ......................................................................................................43
7.2.35
MSI CAPABILITY ID REGISTER – OFFSET 8Ch (Downstream Port Only) .................................... 43
7.2.36
NEXT ITEM POINTER REGISTER – OFFSET 8Ch (Downstream Port Only) ................................. 43
7.2.37
MESSAGE CONTROL REGISTER – OFFSET 8Ch (Downstream Port Only) .................................. 43
7.2.38
MESSAGE ADDRESS REGISTER – OFFSET 90h (Downstream Port Only) .................................... 44
7.2.39
MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h (Downstream Port Only) ...................... 44
7.2.40
MESSAGE DATA REGISTER – OFFSET 98h (Downstream Port Only) ........................................... 44
7.2.41
VPD CAPABILITY ID REGISTER – OFFSET 9Ch (Upstream Port Only)........................................ 44
7.2.42
NEXT ITEM POINTER REGISTER – OFFSET 9Ch (Upstream Port Only) ...................................... 44
7.2.43
VPD REGISTER – OFFSET 9Ch (Upstream Port Only).................................................................... 44
7.2.44
VPD DATA REGISTER – OFFSET A0h (Upstream Port Only)......................................................... 45
7.2.45
VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h .................................................. 45
7.2.46
NEXT ITEM POINTER REGISTER – OFFSET A4h .......................................................................... 45
7.2.47
LENGTH REGISTER – OFFSET A4h ................................................................................................ 45
7.2.48
XPIP CSR0 – OFFSET A8h (Test Purpose Only)............................................................................... 45
7.2.49
XPIP CSR1 – OFFSET ACh (Test Purpose Only) .............................................................................. 46
7.2.50
REPLAY TIME-OUT COUNTER – OFFSET B0h .............................................................................. 46
7.2.51
ACKNOWLEDGE LATENCY TIMER – OFFSET B0h....................................................................... 46
7.2.52
SWITCH OPERATION MODE – OFFSET B4h (Upstream Port)...................................................... 46
7.2.53
SWITCH OPERATION MODE – OFFSET B4h (Downstream Port) ................................................. 48
7.2.54
SSID/SSVID CAPABILITY ID REGISTER – OFFSET B8h ................................................................ 48
7.2.55
NEXT ITEM POINTER REGISTER – OFFSET B8h .......................................................................... 48
7.2.56
SUBSYSTEM VENDOR ID REGISTER – OFFSET BCh.................................................................... 48
7.2.57
SUBSYSTEM ID REGISTER – OFFSET BCh .................................................................................... 49
7.2.58
GPIO CONTROL REGISTER – OFFSET D8h (Upstream Port Only)............................................... 49
7.2.59
EEPROM CONTROL REGISTER – OFFSET DCh (Upstream Port Only)........................................ 50
相關(guān)PDF資料
PDF描述
PI7C9X20508GPBNDE IC PCIE PACKET SWITCH 256BGA
PI7C9X440SLBFDE IC PCIE-TO-USB 2.0 CTRLR 128LQFP
PI7C9X442SLBFDE IC PCIE-TO-USB2.0 SWIDGE 128LQFP
PI7C9X7952AFDE IC PCIE-TO-UART BRIDGE 128LQFP
PI7C9X7954AFDE IC PCIE-TO-UART BRIDGE 128LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C9X20508GPANDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube
PI7C9X20508GPBEVB 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20508GPBNDE 功能描述:外圍驅(qū)動器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20508GPNDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Trays
PI7C9X2G303ELAEVB 制造商:Pericom Semiconductor Corporation 功能描述:Switch IC Development Tools Eval Kit for PI7C9X2G303ELA
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*