TM Family Datasheet Page 16 of 81 June 2009 – " />
參數(shù)資料
型號(hào): PI7C9X20505GPBNDE
廠商: Pericom
文件頁數(shù): 8/81頁
文件大?。?/td> 0K
描述: IC PCIE PACKET SWITCH 256BGA
產(chǎn)品變化通告: Copper Wire Change 26/Sept/2011
標(biāo)準(zhǔn)包裝: 90
系列: GreenPacket™
應(yīng)用: 封裝開關(guān),5 端口/5 線道
接口: PCI Express
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X20505GP
5Port-5Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 16 of 81
June 2009 – Revision 1.5
Pericom Semiconductor
4 PIN ASSIGNMENTS
4.1
PIN LIST of 256-PIN PBGA
PIN
NAME
PIN
NAME
PIN
NAME
PIN
NAME
A1
VTT
E1
NC
J1
SLOTCLK[2]
N1
DTX[3]
A2
VTT
E2
NC
J2
VSS
N2
DEQ[0]
A3
NC
E3
VDDCAUX
J3
SLOTCLK[3]
N3
VSS
A4
VSS
E4
RESET_L
J4
VDDR
N4
DEQ[1]
A5
NC
E5
DWNRST_L[4]
J5
GPIO[0]
N5
DEQ[2]
A6
VSS
E6
DWNRST_L[2]
J6
GPIO[1]
N6
VDDC
A7
NC
E7
TEST5
J7
VDDC
N7
ATT_IND[3]
A8
VDDCAUX
E8
TEST4
J8
VSS
N8
VDDC
A9
NC
E9
VDDC
J9
VSS
N9
MRL_PDC[3]
A10
VTT
E10
VDDC
J10
VSS
N10
PWR_ENA_L[3]
A11
PETP[0]
E11
VDDA
J11
VDDA
N11
PWR_FLT[3]
A12
VSS
E12
VDDR
J12
VDDC
N12
PORTERR[1]
A13
PERP[0]
E13
VSS
J13
VDDA
N13
PORTERR[4]
A14
VSS
E14
TEST6
J14
VSS
N14
SCAN_EN
A15
REFCLKN
E15
VSS
J15
VSS
N15
VDDCAUX
A16
REFCLKP
E16
VSS
J16
VSS
N16
VSS
B1
NC
F1
VAUX
K1
VSS
P1
DEQ[3]
B2
VSS
F2
WAKEUP_L
K2
GPIO[2]
P2
VSS
B3
NC
F3
NC
K3
GPIO[3]
P3
RXEQCTL[0]
B4
VSS
F4
VC1_EN
K4
GPIO[4]
P4
RXEQCTL[1]
B5
NC
F5
VSS
K5
GPIO[5]
P5
VDDR
B6
VSS
F6
VDDC
K6
VDDC
P6
PWR_IND[3] /
SLOTCLK[4]
B7
NC
F7
VDDC
K7
VSS
P7
ATT_IND[2]
B8
VSS
F8
VDDC
K8
VDDC
P8
ATT_BTN[2]
B9
NC
F9
VDDC
K9
VSS
P9
MRL_PDC[2]
B10
VTT
F10
VDDC
K10
VDDC
P10
VSS
B11
PETN[0]
F11
VDDA
K11
TRST_L
P11
PWR_FLT[2]
B12
VSS
F12
NC
K12
VDDC
P12
PORTERR[0]
B13
PERN[0]
F13
NC
K13
VDDR
P13
PORTERR[3]
B14
VSS
F14
VSS
K14
VSS
P14
EEPD
B15
VSS
F15
PETP[4]
K15
PERN[3]
P15
PETN[2]
B16
VSS
F16
PETN[4]
K16
PERP[3]
P16
PETP[2]
C1
NC
G1
SLOT_IMP[1]
L1
GPIO[6]
R1
TXTERMADJ[0]
C2
VSS
G2
SLOT_IMP[2]
L2
GPIO[7]
R2
RXTERMADJ[0]
C3
VSS
G3
VDDR
L3
VDDR
R3
NC
C4
VSS
G4
SLOT_IMP[3]
L4
TEST1
R4
VSS
C5
VSS
G5
VDDC
L5
VDDC
R5
NC
C6
VDDR
G6
VSS
L6
HIDRV
R6
PWR_IND[2] /
HOTPLUG[4]
C7
VSS
G7
VDDC
L7
ATT_IND[4]
R7
ATT_IND[1]
C8
VSS
G8
VSS
L8
ATT_BTN[4]
R8
ATT_BTN[1]
C9
VSS
G9
VSS
L9
MRL_PDC[4]
R9
MRL_PDC[1]
C10
VSS
G10
VDDA
L10
VDDC
R10
PWR_ENA_L[2]
C11
VSS
G11
VDDA
L11
VDDC
R11
PWR_FLT[1]
C12
VSS
G12
VDDC
L12
TCK
R12
VSS
C13
VSS
G13
VDDC
L13
TMS
R13
VDDR
C14
VSS
G14
VDDR
L14
TDI
R14
EECLK
C15
VSS
G15
VTT
L15
VSS
R15
VTT
C16
VSS
G16
VTT
L16
VSS
R16
VTT
D1
VSS
H1
HOTPLUG[2]
M1
VSS
T1
VDDR
D2
VSS
H2
HOTPLUG[3]
M2
LODRV
T2
TXTERMADJ[1]
D3
VDDCAUX
H3
SLOTCLK[0]
M3
DTX[0]
T3
RXTERMADJ[1]
D4
TEST2
H4
HOTPLUG[1]
M4
VDDR
T4
SMBCLK
D5
DWNRST_L[3]
H5
SLOTCLK[1]
M5
DTX[1]
T5
SMBDATA
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