參數資料
| 型號： | PI7C9X7952AFDE |
| 廠商： | Pericom |
| 文件頁數： | 19/68頁 |
| 文件大小： | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標準包裝： | 90 |
| 應用： | PCIe至UART橋接 |
| 接口： | 高級配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應商設備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X7952
PCI Express Dual UART
Datasheet
Page 26 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
Reset to 0b.
20
Capabilities List
RO
Set to 1 to enable support for the capability list (offset 34h is the
pointer to the data structure)
Reset to 1b.
21
66MHz Capable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
22
Reserved
RO
Reset to 0b.
23
Fast Back-to-Back
Capable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
24
Master Data Parity
Error
RWC
It is not implemented. Hardwired to 0b.
26:25
DEVSEL# Timing
RO
Does not apply to PCI Express. Must be hardwired to 0b.
27
Signaled Target
Abort
RWC
Set to 1 (by a completer) whenever completing a request in the I/O
bridge side using Completer Abort Completion Status.
Reset to 0b.
28
Received Target
Abort
RWC
It is not implemented. Hardwired to 0b.
29
Received Master
Abort
RWC
It is not implemented. Hardwired to 0b.
30
Signaled System
Error
RWC
Set to 1 when the I/O bridge sends an ERR_FATAL or
ERR_NONFATAL Message, and the SERR Enable bit in the
Command register is 1.
Reset to 0b.
31
Detected Parity
Error
RWC
Set to 1 whenever the I/O bridge receives a Poisoned TLP.
Reset to 0b.
6.2.5.
REVISION ID REGISTER – OFFSET 08h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Revision
RO
Indicates revision number of the I/O bridge. The default value may
be changed by auto-loading from EEPROM.
Reset to 00h.
6.2.6.
CLASS CODE REGISTER – OFFSET 08h
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Programming
Interface
RO
Read as 02h to indicate no programming interfaces have been
defined for PCI-to-PCI bridges
23:16
Sub-Class Code
RO
Read as 00h to indicate device is PCI-to-PCI bridge
31:24
Base Class Code
RO
Read as 07h to indicate device is a bridge device
6.2.7.
CACHE LINE REGISTER – OFFSET 0Ch
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Cache Line Size
RW
The cache line size register is set by the system firmware and the
operating system to system cache line size. This field is implemented
by PCI Express devices as a RW field for legacy compatibility
purposes but has no impact on any PCI Express device functionality.
Reset to 00h.
6.2.8.
MASTER LATENCY TIMER REGISTER – OFFSET 0Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Latency timer
RO
Does not apply to PCI Express. Must be hardwired to 00h.
13-0092
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