Pericom Semiconductor BIT FUNCTION TYPE DESCRIPTION 5 RTS Inte" />
參數(shù)資料
型號: PI7C9X7952AFDE
廠商: Pericom
文件頁數(shù): 39/68頁
文件大小: 0K
描述: IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝: 90
應(yīng)用: PCIe至UART橋接
接口: 高級配置電源接口(ACPI)
電源電壓: 1.8V, 3.3V
封裝/外殼: 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X7952
PCI Express Dual UART
Datasheet
Page 44 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
5
RTS Interrupt
RW
0b: Disable RTS/DTR Interrupt
1b: Enable RTS/DTR Interrupt
Reset to 0b.
6
CTS Interrupt
RW
0b: Disable CTS/DSR interrupt
1b: Enable CTS/DSR interrupt
Reset to 0b.
7
Reserved
RW
7.1.4.
INTERRUPT STATUS REGISTER – OFFSET 02h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Interrupt Status
RO
0b: An interrupt is pending
1b: No interrupt pending
Reset to C1h.
Priority
Level
Interrupt Status Bits
Interrupt Source
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
Rx data error
2
1
0
1
0
Rx data available
3
1
0
1
0
Rx time-out
4
1
0
1
0
Tx FIFO empty
5
1
0
Modem status change
6
1
0
1
0
Xoff or special
character detected
7
1
0
CTS or RTS state
changed
X
1
0
1
No interrupt pending
7.1.5.
FIFO CONTROL REGISTER – OFFSET 02h
BIT
FUNCTION
TYPE
DESCRIPTION
0
FIFO Mode Enable
WO
0b: Disable the FIFO mode
1b: Enable the FIFO mode
Reset to 0b.
1
Rx FIFO Flush
WO
0b: No action
1b: Reset the receive FIFO, self-clear after resetting the FIFO
Reset to 0b.
2
Tx FIFO Flush
WO
0b: No action
1b: Reset the transmit FIFO, self-clear after resetting the FIFO
Reset to 0b.
3
Reserved
WO
Reset to 0b.
5:4
Tx Trigger Level
WO
In the Enhanced Mode.
00b: 16
01b: 32
10b: 64
11b: 112
Reset to 00b.
7:6
Rx Trigger Level
WO
In the Non-Enhanced mode
00b: 1
01b: 4
10b: 8
11b: 14
In the Enhanced mode
00b: 15
01b: 31
10b: 63
11b: 111
Reset to 00b.
13-0092
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