Pericom Semiconductor 6.2.49. PCI EXPRESS CAPABILITIES REGI" />
參數(shù)資料
型號： PI7C9X7952AFDE
廠商： Pericom
文件頁數(shù)： 28/68頁
文件大?。?/td> 0K
描述： IC PCIE-TO-UART BRIDGE 128LQFP
標準包裝： 90
應(yīng)用： PCIe至UART橋接
接口： 高級配置電源接口（ACPI）
電源電壓： 1.8V, 3.3V
封裝/外殼： 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X7952
PCI Express Dual UART
Datasheet
Page 34 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
6.2.49. PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h
BIT
FUNCTION
TYPE
DESCRIPTION
19:16
Capability Version
RO
Read as 0001b to indicate the I/O bridge is compliant to Revision
1.0a of PCI Express Base Specifications.
23:20
Device/Port Type
RO
Indicates the type of Legacy PCI Express Endpoint device.
Reset to 1h.
24
Slot Implemented
RO
It is not implemented. Hardwired to 0b.
29:25
Interrupt Message
Number
RO
It is not implemented. Hardwired to 00000b.
31:30
Reserved
RO
Reset to 00b.
6.2.50. DEVICE CAPABILITIES REGISTER – OFFSET E4h
BIT
FUNCTION
TYPE
DESCRIPTION
2:0
Max_Payload_Size
Supported
RO
Indicates the maximum payload size that the I/O bridge can support
for TLPs. The I/O bridge supports 128 bytes max payload size.
Reset to000b.
4:3
Phantom Functions
Supported
RO
It is not implemented. Hardwired to 00b.
5
Extended Tag Field
Supported
RO
It is not implemented. Hardwired to 0b.
8:6
Endpoint L0s
Acceptable Latency
RO
Acceptable total latency that an Endpoint can withstand due to the
transition from L0s state to the L0 state.
Reset to 000b.
11:9
Endpoint L1
Acceptable Latency
RO
Acceptable total latency that an Endpoint can withstand due to the
transition from L1 state to the L0 state.
Reset to 000b.
12
Attention Button
Present
RO
It is not implemented. Hardwired to 0b.
13
Attention Indicator
Present
RO
It is not implemented. Hardwired to 0b.
14
Power Indicator
Present
RO
It is not implemented. Hardwired to 0b.
15
Role_Base Error
Reporting
RO
When set, indicated that the device implements the functionality
originally defined in the Error Reporting ECN. The default value
may be changed by auto-loading from EEPROM.
Reset to 1b.
17:16
Reserved
RO
Reset to 00b.
25:18
Captured Slot Power
Limit Value
RO
In combination with the Slot Power Limit Scale value, specifies the
upper limit on power supplied by slot.
This value is set by the Set_Slot_Power_Limit message or
hardwired to “00h”.
Reset to 00b.
27:26
Captured Slot Power
Limit Scale
RO
Specifies the scale used for the Slot Power Limit Value.
This value is set by the Set_Slot_Power_Limit message or
hardwired to “00b”.
Reset to 00b.
31:28
Reserved
RO
Reset to 0h.
6.2.51. DEVICE CONTROL REGISTER – OFFSET E8h
BIT
FUNCTION
TYPE
DESCRIPTION
13-0092
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參數(shù)描述
PI7C9X7952AFDEX 制造商:Pericom Semiconductor Corporation 功能描述:
PI7C9X7954AEVB 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD PI7C9X7954/52A
PI7C9X7954AFDE 功能描述:外圍驅(qū)動器與原件 - PCI X1 PCIE-UART 4 Channel Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X7958AEVB 制造商:Pericom Semiconductor Corporation 功能描述:7958A EVAL BOARD 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD PI7C9X7958A 制造商:Pericom Semiconductor Corporation 功能描述:8 Port PCI Express UART I/O Bridge Evaluation Board
PI7C9X7958ANBE 功能描述:外圍驅(qū)動器與原件 - PCI X1 PCIE-UART 8 Channel Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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